Tiny GPU Unit 🎮

A minimal, educational GPU implementation in Verilog that demonstrates the fundamentals of graphics processing and VGA display generation. Perfect for learning digital design, FPGA development, and computer graphics basics!

✨ What is This?

This project implements a tiny graphics processing unit that can:

• Draw pixels, lines, and rectangles
• Generate proper VGA timing signals
• Manage a frame buffer
• Process graphics commands

It's like building your own miniature graphics card from scratch! 🖥️

🚀 Quick Start

Simulation (See it work virtually):

# 1. Install Icarus Verilog
sudo apt install iverilog gtkwave

# 2. Clone this repo
git https://github.com/Uper6/bit_gpu.git
cd bit_gpu

# 3. Run the simulation
make simulate

# 4. View waveforms (optional)
make wave   

FPGA (See it on real hardware):

# Program your FPGA board
make program

🎯 What Can It Do?

🎨 Graphics Primitives

// Clear screen to blue
send_command(CMD_CLEAR, COLOR_BLUE, 0, 0, 0);

// Draw a red pixel at (100, 100)  
send_command(CMD_DRAW_PIXEL, 100, 100, COLOR_RED, 0);

// Draw green line from (50,50) to (150,150)
send_command(CMD_DRAW_LINE, 50, 50, 150, 150, COLOR_GREEN);

// Draw white rectangle outline
send_command(CMD_DRAW_RECT, 200, 50, 50, 30, COLOR_WHITE);

📺 VGA Output

• 320x240 resolution (classic retro feel!)
• 60Hz refresh rate (smooth display)
• RGB565 color (65,536 colors)
• Standard VGA timing (works with most monitors)

🔧 How It Works

The Pipeline:

1. Command Processor - Receives drawing instructions
2. Graphics Engine - Renders pixels/lines/shapes
3. Frame Buffer - Stores the current image
4. VGA Controller - Outputs pixels to display

State Machine Magic:

// The GPU knows what to do!
STATE_IDLE    // Waiting for commands
STATE_CLEAR   // Clearing the screen  
STATE_PIXEL   // Drawing pixels
STATE_LINE    // Drawing lines (using Bresenham's algorithm)
STATE_RECT    // Drawing rectangles

🧪 Testing & Verification

We've included a comprehensive testbench that automatically verifies everything works:

=== Test 1: Clear Screen ===
✅ Screen cleared successfully!

=== Test 2: Draw Pixel ===  
✅ Red pixel drawn at (100, 100)!

=== Test 3: Draw Line ===
✅ Line drawn using Bresenham's algorithm!

=== Test Summary ===
Passed: 6/6  🎉
All graphics operations working correctly!

🛠️ Hardware Requirements

For Simulation:

• Linux/WSL with Icarus Verilog
• GTKWave for waveform viewing (optional)

For FPGA Deployment:

• FPGA board with VGA output (Basys 3, DE1-SoC, etc.)
• VGA monitor (or VGA-to-HDMI adapter)
• Quartus Prime (Intel) or Vivado (Xilinx) tools

🎓 Learning Outcomes

By exploring this project, you'll understand:

• VGA timing and signal generation ⏱️
• Frame buffer management 🖼️
• Graphics algorithms (Bresenham's line drawing) 📐
• FPGA design and verification 🔍
• Hardware/software co-design 🤝

🚀 Getting Hands-On

Want to see it in action?

1. Start with simulation - No hardware needed!
2. Modify the test patterns in tb_bit_gpu.v
3. Add new features like circles or triangles
4. Run on FPGA to see real VGA output

Example Modification:

// Try adding this to draw a cool pattern!
for (int x = 0; x < 320; x = x + 10) {
    draw_line(x, 0, 320-x, 239, rainbow_colors[x % 7]);
}

🤝 Contributing

Found a bug? Want to add features? Awesome!

• 🐛 Report issues - Help us squash bugs
• 💡 Suggest features - What should we add next?
• 🔧 Submit PRs - Add your own improvements
• 📚 Improve docs - Make it clearer for others

🎯 Roadmap

• Triangle rendering
• Sprite support
• Hardware acceleration
• HDMI output
• 3D transformation pipeline

📄 License

MIT License - feel free to use this in your own projects and learning!

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