System Verilog Tutorial

this repository contains my Verilog projects and links to access them.

Catalyst N2 — Neuromorphic processor with compartmental neurons, microcode learning, synaptic delays. Verilog RTL, FPGA validated. Apache 2.0.

AXI-4 DMA Controller

Single Instruction Multiple Threads GPU Core with textbook Streaming Multi-Processor features

3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism

SystemVerilog language-oriented exercises

Catalyst N1 — Open source neuromorphic processor (Loihi 1 parity). 128 cores, 131K neurons, 14-opcode learning ISA, FPGA-validated on AWS F2.

HDL libraries and projects

我设计了一些数字集成电路的教学实验，供大家学习~

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

An open education resource Digital Design textbook

This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.

tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.

Open source FPGA-based NIC and platform for in-network compute

A simple implementation of a UART modem in Verilog.

Some design examples of Verilog about digital circuits

AMBA bus lecture material

Verilog RTL Design

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

Greyhound on IHP SG13G2 0.13 μm BiCMOS process

Multi-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench

A mixed-signal test project on Tiny Tapeout

4 stage, in-order, compute RISC-V core based on the CV32E40P

BenchVolt PD is an open-source, USB-C powered multi-channel lab power supply delivering up to 100 W. Features 5 outputs (0 V–32 V), STM32 control, USB-PD, low-noise LDOs, and a Python GUI. Compact,…

数字IC相关资料

This is a repository containing solutions to the problem statements given in HDL Bits website.

Verilog and VHDL for book

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …