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A next.js web application that integrates AI capabilities with draw.io diagrams. This app allows you to create, modify, and enhance diagrams through natural language commands and AI-assisted visual…
Fast and memory-efficient exact attention
hardware implementation of transformers running microgpt at 50k+ tkps
Open-source, low-cost 10.5 GHz PLFM phased array RADAR system
A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。
This is the PyTorch implementation of our paper: Unsupervised underwater shipwreck detection in side-scan sonar images based on domain-adaptive techniques
A FPGA friendly 32 bit RISC-V CPU implementation
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
An open-source 2D battle royale game inspired by surviv.io. Work in progress.
Auto-configure and then control your Midea M-Smart devices (Air conditioner, Fan, Water heater, Washer, etc) via local area network.
Auto-configure and then control your Midea M-Smart devices (Air conditioner, Fan, Water heater, Washer, etc) via local area network.
☁️ Ultra-fast, secure & lightweight self-hosted cloud storage — your files, photos, calendars & contacts, all in one place. Built in Rust.
etlp - Emby/Jellyfin 调用外部本地播放器，并回传播放记录。适配 Plex。
Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.
An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
Vim mode for VSCode, powered by Neovim
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This repository is a mirror of https://git.openwrt.org/openwrt/openwrt.git It is for reference only and is not active for check-ins. We will continue to accept Pull Requests here. They will be merg…
Proxmox VE Helper-Scripts (Community Edition)
The Free Software Media System - Server Backend & API
ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.
All in one vscode plugin for HDL development
Implement a bitonic sorting network on FPGA