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IR support for switch instructions#7536

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vaivaswatha wants to merge 27 commits intomasterfrom
vaivaswatha/ir_switch
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IR support for switch instructions#7536
vaivaswatha wants to merge 27 commits intomasterfrom
vaivaswatha/ir_switch

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Description

This PR adds a new IR instruction switch, that supports both exhaustive (for exhaustive matchs, verified by the front-end) and non-exhaustive switches.

Since matchs in the frontend still translate to an if-else ladder, a switch is never generated yet. So for testing, I've added support in the test harness to compile and execute (in the VM) sway-ir files directly.

@vaivaswatha vaivaswatha self-assigned this Jan 21, 2026
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codspeed-hq bot commented Jan 21, 2026

Merging this PR will not alter performance

✅ 25 untouched benchmarks


Comparing vaivaswatha/ir_switch (9988e37) with master (0d8fbc8)

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@vaivaswatha vaivaswatha marked this pull request as ready for review January 22, 2026 10:30
@vaivaswatha vaivaswatha requested review from a team as code owners January 22, 2026 10:30
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cursor bot commented Jan 22, 2026

PR Summary

Medium Risk
Touches core IR semantics and Fuel backend lowering (including data-section encoding), which can affect codegen correctness; EVM support is stubbed (todo!()), reducing scope but requiring care to avoid accidental execution paths.

Overview
Adds a new switch terminator to sway-ir (parser/printer, block successor handling, verifier errors + validation rules, and multiple optimization/analysis passes) and wires it through Fuel backend codegen.

Fuel asm generation now lowers switch via a jump-table style OrganizationalOp::Switch, including new data-section support for WordArray entries (byte emission, display/debug printing, size accounting, and constant-prop/basic-block boundary updates). EVM codegen is plumbed to recognize switch but the lowering is still todo!().

Testing is extended with an ir_run e2e category that compiles and executes main.ir directly via new forc_pkg::compile_ir, plus new IR switch test programs and CFG simplification tests.

Written by Cursor Bugbot for commit 9988e37. This will update automatically on new commits. Configure here.

xunilrj
xunilrj previously approved these changes Jan 23, 2026
tritao
tritao previously approved these changes Jan 26, 2026
xunilrj
xunilrj previously approved these changes Jan 27, 2026
@vaivaswatha vaivaswatha dismissed stale reviews from xunilrj and tritao via 0d574ce February 3, 2026 07:35
@ironcev ironcev self-assigned this Feb 10, 2026
@ironcev ironcev added compiler General compiler. Should eventually become more specific as the issue is triaged compiler: ir IRgen and sway-ir including optimization passes compiler: codegen Everything to do with IR->ASM, register allocation, etc. labels Feb 10, 2026
@ironcev ironcev disabled auto-merge February 10, 2026 17:29
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fuel-cla-bot bot commented Feb 16, 2026

Thanks for the contribution! It looks like @vaivaswatha is an internal user so signing the CLA is not required. However, they are not a member of this GitHub org so we can't confirm this.

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fuel-cla-bot bot commented Feb 17, 2026

Thanks for the contribution! Unfortunately we can't verify the commit author(s): Vaivaswatha Nagaraj <v***@f***.sh> Vaivaswatha N <v***@f***.sh>. One possible solution is to add that email to your GitHub account. Alternatively you can change your commits to another email and force push the change. After getting your commits associated with your GitHub account, refresh the status of this Pull Request.

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Cursor Bugbot has reviewed your changes and found 1 potential issue.

Bugbot Autofix is OFF. To automatically fix reported issues with Cloud Agents, enable Autofix in the Cursor dashboard.

sorted_cases
.iter_mut()
.for_each(|(val, _)| *val -= min_case_value);
}
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In-place SUBI corrupts discriminant register for successor blocks

High Severity

The SUBI writes the adjusted discriminant back into discrim_reg, the same virtual register returned by value_to_register(discriminant). This register is shared by all uses of that IR value. If any successor block references the discriminant directly (not via phi/block arguments), value_to_register returns the same register, and the successor sees the subtracted value instead of the original. A fresh temporary register from self.reg_seqr.next() is needed for the adjusted value.

Fix in Cursor Fix in Web

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cla:signed compiler: codegen Everything to do with IR->ASM, register allocation, etc. compiler: ir IRgen and sway-ir including optimization passes compiler General compiler. Should eventually become more specific as the issue is triaged

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