I'm Jeevanandh R, an aspiring RTL Design Engineer with a vision to design reliable, efficient, and scalable digital logic systems. I thrive in the low-level digital world, translating functional ideas into real hardware through Verilog/SystemVerilog.
🔍 My core passion lies in:
- Architecting custom processors and pipelines
- Crafting clean RTL modules with synthesizable code
- Writing powerful testbenches and performing waveform-level debugging
- Staying up-to-date with trends in ASIC/FPGA design and verification
💡 With additional knowledge in embedded systems and web dev, I love combining RTL with higher-level systems to bring ideas to life in the real world.
🧠 Currently focused on:
- RISC-V architecture & implementation
- Pipelined designs with hazard mitigation
- UART + FIFO and communication controller Designs
🚀 "Designing logic that ticks at the heart of tomorrow’s tech."
- ✅ Verilog HDL, SystemVerilog
- ✅ Icarus Verilog, GTKWave, ModelSim
- ✅ FSM Design, Testbenches, Pipelining, Hazard Handling
- ✅ Digital Design Fundamentals (MUX, RAM, ALU, etc.)
- ✅ Synthesis Concepts and Timing Analysis
- 🔧 RISC-V 5-stage Pipelined CPU with Hazard Detection
- 🔧 RAM Modules with Testbenching
- 🔧 ALU + Control Unit Design for Custom ISA
- ✅ ESP32 Programming via Arduino IDE & PlatformIO
- ✅ Sensor Integration: PIR, DHT11, Photoresistor, OLED
- ✅ UI Systems: Scroll Menus, EEPROM Settings, Relay Control
- ✅ Real-time Multisensor Systems & Data Transmission
- ✅ React.js + Tailwind CSS UI Development
- ✅ Node.js, Express & MongoDB Backend Systems
- ✅ Razorpay Integration for SaaS Billing
- ✅ OTP Auth, Secure Token Storage, File Uploads
- 💻 Hostel/PG Management SaaS
- 🎧 MoodTunes – Music by Emotion
⭐ Open to internships and collaboration in the RTL/VLSI domain. Let’s build silicon magic together!