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Merged
poemonsense merged 4 commits into from
Mar 5, 2021
Merged

RS: fix some typo && optimize deq logic for performance #639

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a9e75c6
RS: optimize numExist signal
Lemover Mar 3, 2021
5abad01
RS: fix some typo
Lemover Mar 3, 2021
8b621a7
RS: optimize deq logic for block-nonfeedback rs
Lemover Mar 4, 2021
fa42f7a
Merge branch 'master' into rs-perf-cnt
Lemover Mar 4, 2021
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16 changes: 8 additions & 8 deletions src/main/scala/xiangshan/XSCore.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -472,14 +472,14 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx
memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.uop.ctrl.commitType)

val itlbRepester = Module(new PTWRepeater())
val dtlbRepester = Module(new PTWRepeater())
itlbRepester.io.tlb <> frontend.io.ptw
dtlbRepester.io.tlb <> memBlock.io.ptw
itlbRepester.io.sfence <> integerBlock.io.fenceio.sfence
dtlbRepester.io.sfence <> integerBlock.io.fenceio.sfence
ptw.io.tlb(0) <> dtlbRepester.io.ptw
ptw.io.tlb(1) <> itlbRepester.io.ptw
val itlbRepeater = Module(new PTWRepeater())
val dtlbRepeater = Module(new PTWRepeater())
itlbRepeater.io.tlb <> frontend.io.ptw
dtlbRepeater.io.tlb <> memBlock.io.ptw
itlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence
dtlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence
ptw.io.tlb(0) <> dtlbRepeater.io.ptw
ptw.io.tlb(1) <> itlbRepeater.io.ptw
ptw.io.sfence <> integerBlock.io.fenceio.sfence
ptw.io.csr <> integerBlock.io.csrio.tlb

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2 changes: 1 addition & 1 deletion src/main/scala/xiangshan/backend/MemBlock.scala
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Expand Up @@ -188,7 +188,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
// exeUnits(i).io.fromInt <> rs.io.deq
rs.io.memfeedback := DontCare

rs.suggestName(s"rsd_${cfg.name}")
rs.suggestName(s"rs_${cfg.name}")

rs
})
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19 changes: 14 additions & 5 deletions src/main/scala/xiangshan/backend/issue/ReservationStation.scala
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Expand Up @@ -126,6 +126,10 @@ class ReservationStation
val ctrl = Module(new ReservationStationCtrl(exuCfg, srcLen, fastPortsCfg, slowPortsCfg, fixedDelay, fastWakeup, feedback))
val data = Module(new ReservationStationData(exuCfg, srcLen, fastPortsCfg, slowPortsCfg, fixedDelay, fastWakeup, feedback))

select.suggestName(s"${this.name}_select")
ctrl.suggestName(s"${this.name}_ctrl")
data.suggestName(s"${this.name}_data")

select.io.redirect := io.redirect
select.io.flush := io.flush
io.numExist := select.io.numExist
Expand Down Expand Up @@ -275,14 +279,17 @@ class ReservationStationSelect
assert(RegNext(!(haveReady && selectPtr >= tailPtr.asUInt)), "bubble should not have valid state like s_valid or s_wait")

// sel bubble
val isFull = Wire(Bool())
val lastbubbleMask = Wire(UInt(iqSize.W))
val bubbleMask = WireInit(VecInit((0 until iqSize).map(i => emptyIdxQueue(i)))).asUInt & lastbubbleMask
// val bubbleIndex = ParallelMux(bubbleMask zip indexQueue) // NOTE: the idx in the indexQueue
val bubblePtr= ParallelPriorityMux(bubbleMask.asBools.zipWithIndex.map{ case (a,i) => (a, i.U)}) // NOTE: the idx of the indexQueue
val findBubble = Cat(bubbleMask).orR
val haveBubble = findBubble && (bubblePtr < tailPtr.asUInt)
val bubbleIndex = indexQueue(bubblePtr)
val bubbleValid = haveBubble && (if (feedback) true.B else !selectValid)
val bubbleValid = haveBubble && (if (feedback) true.B
else if (nonBlocked) !selectValid
else Mux(isFull, true.B, !selectValid))
val bubbleReg = RegNext(bubbleValid)
val bubblePtrReg = RegNext(Mux(moveMask(bubblePtr), bubblePtr-1.U, bubblePtr))
lastbubbleMask := ~Mux(bubbleReg, UIntToOH(bubblePtrReg), 0.U) &
Expand All @@ -292,8 +299,9 @@ class ReservationStationSelect
// deq
val dequeue = if (feedback) bubbleReg
else bubbleReg || issueFire
val deqPtr = if (feedback) bubblePtrReg
else Mux(selectReg, selectPtrReg, bubblePtrReg)
val deqPtr = if (feedback) bubblePtrReg
else if (nonBlocked) Mux(selectReg, selectPtrReg, bubblePtrReg)
else Mux(bubbleReg, bubblePtrReg, selectPtrReg)
moveMask := {
(Fill(iqSize, 1.U(1.W)) << deqPtr)(iqSize-1, 0)
} & Fill(iqSize, dequeue)
Expand Down Expand Up @@ -349,7 +357,7 @@ class ReservationStationSelect
}

// enq
val isFull = tailPtr.flag
isFull := tailPtr.flag
// agreement with dispatch: don't fire when io.redirect.valid
val enqueue = io.enq.fire() && !(io.redirect.valid || io.flush)
val tailInc = tailPtr + 1.U
Expand All @@ -372,7 +380,7 @@ class ReservationStationSelect
io.deq.valid := selectValid
io.deq.bits := selectIndex

io.numExist := RegNext(Mux(nextTailPtr.flag, (iqSize-1).U, nextTailPtr.value))
io.numExist := RegNext(Mux(nextTailPtr.flag, if(isPow2(iqSize)) (iqSize-1).U else iqSize.U, nextTailPtr.value))

assert(RegNext(Mux(tailPtr.flag, tailPtr.value===0.U, true.B)))
}
Expand Down Expand Up @@ -495,6 +503,7 @@ class ReservationStationCtrl
sqIdx(enqPtr) := enqUop.sqIdx
}
ldWait.suggestName(s"${this.name}_ldWait")
sqIdx.suggestName(s"${this.name}_sqIdx")
io.readyVec := srcQueue.map(Cat(_).andR).zip(ldWait).map{ case (s, l) => s&l }
}

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