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base repository: PyHDI/Pyverilog
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base: 1.2.1
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head repository: PyHDI/Pyverilog
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compare: master
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  • 10 commits
  • 29 files changed
  • 2 contributors

Commits on May 22, 2020

  1. Fixed the import path for pyverilog version.

    @shtaxxx
    shtaxxx committed May 22, 2020
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  2. Included PLY is removed.

    @shtaxxx
    shtaxxx committed May 22, 2020
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  3. plyparser.py is removed

    @shtaxxx
    shtaxxx committed May 22, 2020
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  4. Updated travis config

    @shtaxxx
    shtaxxx committed May 22, 2020
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Commits on Aug 22, 2020

  1. Feature addition: Verilog code in Python strings along with verilog f… 

    …iles.

The current API is such that it takes in a (list of) file(s) as input. However,
when embedding Pyverilog in aother python libraries/code, it would be helpful
to pass python sitrings directly to the API rather than files.

This feature works along with the current implementation in such a way that
the user can either continue passing files as inputs as in the existing API
or pass verilog code in python strings to the API.
    @ndyashas
    ndyashas committed Aug 22, 2020
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Commits on Dec 14, 2020

  1. 'reorder' argument is renamed as 'do_reorder' to avoid the naming con… 

    …flict.
    @shtaxxx
    shtaxxx committed Dec 14, 2020
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  2. Merge branch 'fix_dataflow_graphgen' into develop

    @shtaxxx
    shtaxxx committed Dec 14, 2020
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  3. Merge pull request #64 from ndyashas/develop 

    Feature addition: Verilog code in Python strings along with verilog files.
    @shtaxxx
    shtaxxx authored Dec 14, 2020
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Commits on Dec 30, 2020

  1. 1.3.0-rc

    @shtaxxx
    shtaxxx committed Dec 30, 2020
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  2. Merge branch 'develop'

    @shtaxxx
    shtaxxx committed Dec 30, 2020
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