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CSA-Project

Performance Modelling - RISC-V processor. This project implements cycle-accurate simulators of a 32-bit RISC-V processor in Python

Command to run

python3 riscv.py --iodir testcases/TC0

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Performance Modelling - RISC-V processor. This project implements cycle-accurate simulators of a 32-bit RISC-V processor in Python

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