two files modified, one file added

tclapp/atrenta/spyglass/app.xml

@@ -2,7 +2,7 @@
 <catalog>
   <apps>
     <app>
-      <revision_history> Updated write_spyglass_script.tcl to correct usage of get_property in some cases. </revision_history>
+      <revision_history> Updated write_spyglass_script.tcl to correct the path for the device libraries. Added the option read_protected_envelope to handle encrypted models. Replaced the exiisting test with a simpler test. </revision_history>
       <name>spyglass</name>
       <pkg_require>Vivado 2015.1</pkg_require>
       <company>atrenta</company>

tclapp/atrenta/spyglass/pkgIndex.tcl

@@ -8,4 +8,4 @@
 # script is sourced, the variable $dir must contain the
 # full path name of this file's directory.
 
-package ifneeded ::tclapp::atrenta::spyglass 1.3 [list source [file join $dir spyglass.tcl]]
+package ifneeded ::tclapp::atrenta::spyglass 1.4 [list source [file join $dir spyglass.tcl]]

tclapp/atrenta/spyglass/spyglass.tcl

@@ -10,7 +10,7 @@ namespace eval ::tclapp::atrenta::spyglass {
     }
 
 }
-package provide ::tclapp::atrenta::spyglass 1.3
+package provide ::tclapp::atrenta::spyglass 1.4
 # this is a comment
 # this is another comment
 # this is a 3rd comment line

tclapp/atrenta/spyglass/test/spy_run.prj

@@ -0,0 +1,58 @@
+read_file -type verilog /global/snps_apps4/vivado_2015.4/Vivado/2015.4/data/verilog/src/glbl.v
+
+set_option lib unisim ./unisim
+set_option lib unimacro ./unimacro
+set_option y /global/snps_apps4/vivado_2015.4/Vivado/2015.4/data/verilog/src/retarget
+set_option y /global/snps_apps4/vivado_2015.4/Vivado/2015.4/data/verilog/src/xeclib
+set_option y /global/snps_apps4/vivado_2015.4/Vivado/2015.4/data/verilog/src/unimacro
+set_option libhdlfiles unisim   /global/snps_apps4/vivado_2015.4/Vivado/2015.4/data/vhdl/src/unisims/unisim_retarget_VCOMP.vhd
+set_option libhdlfiles unimacro /global/snps_apps4/vivado_2015.4/Vivado/2015.4/data/vhdl/src/unimacro/unimacro_VCOMP.vhd
+
+read_file -type gateslib /global/snps_apps4/vivado_2015.4/Vivado/2015.4/data/parts/xilinx/kintex7/devint/kintex7.lib
+
+
+
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/meta_harden.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/debouncer.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/uart_tx_ctl.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/out_ddr_flop.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/reset_bridge.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/uart_rx_ctl.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/clk_div.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/to_bcd.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/uart_baud_gen.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/clk_gen.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/cmd_parse.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/dac_spi.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/lb_ctl.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/rst_gen.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/samp_gen.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/samp_ram.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/uart_rx.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/clkx_bus.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/resp_gen.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/uart_tx.v 
+read_file -type verilog /remote/vgrnd99/alokedas/static/FPGA/tcl_app/tc_from_ravi/project_1/project_1.srcs/sources_1/imports/Sources/kintex7/wave_gen.v 
+
+set_option stop {BRAM_TDP_MACRO}
+set_option enable_save_restore no
+set_option enable_pass_exit_codes true
+set_option projectwdir sg_results
+set_option libext { .v .sv .vhd .vh }
+set_option work WORK
+set_option enableSV yes
+set_option language_mode mixed
+set_option pragma { synopsys synthesis }
+set_option disable_hdllibdu_lexical_checks yes
+set_option top wave_gen
+#set_option prefer_tech_lib yes
+set_option enable_auto_infer_bus_pins yes
+set_option read_protected_envelope yes
+set_option enable_fpga yes
+
+
+current_methodology $SPYGLASS_HOME/GuideWare2.0/block/rtl_handoff
+
+current_goal cdc/cdc_setup
+set_goal_option addrules Setup_blackbox01
+

tclapp/atrenta/spyglass/test/spyglass_tclapp_test.tcl

@@ -0,0 +1,13 @@
+create_project project_1 ./project_1 -part xc7k70tfbg676-1 -force
+set_property target_language VHDL [current_project]
+
+instantiate_example_design -template xilinx.com:design:wave_gen:1.0  
+
+update_compile_order -fileset sources_1
+update_compile_order -fileset sim_1
+
+source $test_dir/../write_spyglass_script.tcl
+
+set design_top [find_top]
+
+::tclapp::atrenta::spyglass::write_spyglass_script $design_top $test_dir/spy_run.prj

tclapp/atrenta/spyglass/test/test.tcl

@@ -5,7 +5,8 @@ set listInstalledApps [::tclapp::list_apps]
 set test_dir [file normalize [file dirname [info script]]]
 puts "== Test directory: $test_dir"
 
-set design_top vfifo_controller
+# ALOKE: 3/12/2016
+#set design_top vfifo_controller
 
 set tclapp_repo [file normalize [file join $test_dir .. .. ..]]
 puts "== Application directory: $tclapp_repo"
@@ -25,15 +26,18 @@ package require ::tclapp::${appName}
 # Start the unit tests
 puts "script is invoked from $test_dir"
 # All the unit test scripts should be sourced now such as:
-if {[catch {source -notrace [file join $test_dir vivado_flow_x4gen2.tcl]} errorstring]} {
+# ALOKE: 3/10/2016: Run a simpler test provided by Ravi
+#if {[catch {source -notrace [file join $test_dir vivado_flow_x4gen2.tcl]} errorstring]} {
+if {[catch {source -notrace [file join $test_dir spyglass_tclapp_test.tcl]} errorstring]} {
   catch { close_project }
 }
 
-::tclapp::atrenta::spyglass::write_spyglass_script $design_top $test_dir/spy_run.prj
+# ALOKE: 3/12/2016: Already part of the above simple test
+#::tclapp::atrenta::spyglass::write_spyglass_script $design_top $test_dir/spy_run.prj
 
 # Cleaning
 close_project
-file delete $test_dir/spy_run.prj
+#file delete $test_dir/spy_run.prj
 #file delete -force $test_dir/vivado_proj_1
 
 # Uninstall the app if it was not already installed when starting the script