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Merged
dbmccrohan merged 2 commits into from
Jul 22, 2016
Merged

Coverage options. #574

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c020403
coverage options
bogdan-aldec Jul 20, 2016
b650f04
tclIndex
bogdan-aldec Jul 21, 2016
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2 changes: 1 addition & 1 deletion tclapp/aldec/activehdl/activehdl.tcl
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Expand Up @@ -12,4 +12,4 @@ namespace eval ::tclapp::aldec::activehdl {
lappend ::auto_path $home
}
}
package provide ::tclapp::aldec::activehdl 1.5
package provide ::tclapp::aldec::activehdl 1.6
2 changes: 1 addition & 1 deletion tclapp/aldec/activehdl/app.xml
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Expand Up @@ -2,7 +2,7 @@
<catalog>
<apps>
<app>
<revision_history>Update 1.5: Separated compilation standard for SystemVerilog.</revision_history>
<revision_history>Update 1.6: Coverage options.</revision_history>
<name>activehdl</name>
<pkg_require>Vivado 2014.1</pkg_require>
<company>aldec</company>
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115 changes: 114 additions & 1 deletion tclapp/aldec/activehdl/common/helpers.tcl
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Expand Up @@ -8,12 +8,125 @@

package require Vivado 1.2014.1

package provide ::tclapp::aldec::common::helpers 1.5
package provide ::tclapp::aldec::common::helpers 1.6

namespace eval ::tclapp::aldec::common {

namespace eval helpers {

proc usf_aldec_appendSimulationCoverageOptions { _optionsList } {
# Summary:
# Argument Usage:
# Return Value:

variable a_sim_vars

upvar $_optionsList optionsList
set fs_obj [get_filesets $a_sim_vars(s_simset)]

set switches ""

if { [get_property [usf_aldec_getPropertyName SIMULATE.STATEMENT_COVERAGE] $fs_obj] } {
append switches "s"
}
if { [get_property [usf_aldec_getPropertyName SIMULATE.BRANCH_COVERAGE] $fs_obj] } {
append switches "b"
}
if { [get_property [usf_aldec_getPropertyName SIMULATE.FUNCTIONAL_COVERAGE] $fs_obj] } {
append switches "f"
}
if { [get_property [usf_aldec_getPropertyName SIMULATE.EXPRESSION_COVERAGE] $fs_obj] } {
append switches "e"
}
if { [get_property [usf_aldec_getPropertyName SIMULATE.CONDITION_COVERAGE] $fs_obj] } {
append switches "c"
}
if { [get_property [usf_aldec_getPropertyName SIMULATE.PATH_COVERAGE] $fs_obj] } {
append switches "p"
}
if { [get_property [usf_aldec_getPropertyName SIMULATE.TOGGLE_COVERAGE] $fs_obj] } {
append switches "t"
}
if { [get_property [usf_aldec_getPropertyName SIMULATE.ASSERTION_COVERAGE] $fs_obj] } {
append switches "a"
}
if { [get_property [usf_aldec_getPropertyName SIMULATE.FSM_COVERAGE] $fs_obj] } {
append switches "m"
}

if { $switches != "" } {
lappend optionsList "-acdb -acdb_cov $switches"
}
}

proc usf_aldec_appendCompilationCoverageOptions { _optionsList compiler } {
# Summary:
# Argument Usage:
# Return Value:

variable a_sim_vars

upvar $_optionsList optionsList
set fs_obj [get_filesets $a_sim_vars(s_simset)]

# -------------- main options -------------

set switches ""

if { [get_property [usf_aldec_getPropertyName COMPILE.STATEMENT_COVERAGE] $fs_obj] } {
append switches "s"
}
if { [get_property [usf_aldec_getPropertyName COMPILE.BRANCH_COVERAGE] $fs_obj] } {
append switches "b"
}
if { [get_property [usf_aldec_getPropertyName COMPILE.EXPRESSION_COVERAGE] $fs_obj] } {
append switches "e"
}
if { [get_property [usf_aldec_getPropertyName COMPILE.CONDITION_COVERAGE] $fs_obj] } {
append switches "c"
}
if { ( $compiler == "acom" || $compiler == "vcom" ) && [get_property [usf_aldec_getPropertyName COMPILE.PATH_COVERAGE] $fs_obj] } {
append switches "p"
}
if { [get_property [usf_aldec_getPropertyName COMPILE.ASSERTION_COVERAGE] $fs_obj] } {
append switches "a"
}
if { [get_property [usf_aldec_getPropertyName COMPILE.FSM_COVERAGE] $fs_obj] } {
append switches "m"
}

if { $switches != "" } {
lappend optionsList "-coverage $switches"
}

# --------- additional options ---------------

set switches ""

if { [get_property [usf_aldec_getPropertyName COMPILE.ENABLE_EXPRESSIONS_ON_SUBPROGRAM_ARGUMENTS] $fs_obj] } {
lappend switches "args"
}
if { [get_property [usf_aldec_getPropertyName COMPILE.ENABLE_ATOMIC_EXPRESSIONS_IN_THE_CONDITIONAL_STATEMENTS] $fs_obj] } {
lappend switches "implicit"
}
if { [get_property [usf_aldec_getPropertyName COMPILE.ENABLE_THE_EXPRESSIONS_CONSISTING_OF_ONE_VARIABLE_ONLY] $fs_obj] } {
lappend switches "onevar"
}
if { [get_property [usf_aldec_getPropertyName COMPILE.ENABLE_THE_EXPRESSIONS_WITH_RELATIONAL_OPERATORS] $fs_obj] } {
lappend switches "relational"
}
if { [get_property [usf_aldec_getPropertyName COMPILE.ENABLE_THE_EXPRESSIONS_RETURNING_VECTORS] $fs_obj] } {
lappend switches "vectors"
}
if { [get_property [usf_aldec_getPropertyName COMPILE.ENABLE_FSM_SEQUENCES_IN_FSM_COVERAGE] $fs_obj] } {
lappend switches "fsmsequence"
}

if { $switches != "" } {
lappend optionsList "-coverage_options [join $switches +]"
}
}

proc usf_aldec_getSimulatorName {} {
# Summary:
# Argument Usage:
Expand Down
4 changes: 2 additions & 2 deletions tclapp/aldec/activehdl/common/pkgIndex.tcl
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Expand Up @@ -8,5 +8,5 @@
# script is sourced, the variable $dir must contain the
# full path name of this file's directory.

package ifneeded ::tclapp::aldec::common::helpers 1.5 [list source [file join $dir helpers.tcl]]
package ifneeded ::tclapp::aldec::common::sim 1.5 [list source [file join $dir sim.tcl]]
package ifneeded ::tclapp::aldec::common::helpers 1.6 [list source [file join $dir helpers.tcl]]
package ifneeded ::tclapp::aldec::common::sim 1.6 [list source [file join $dir sim.tcl]]
10 changes: 7 additions & 3 deletions tclapp/aldec/activehdl/common/sim.tcl
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Expand Up @@ -8,9 +8,9 @@

package require Vivado 1.2014.1

package require ::tclapp::aldec::common::helpers 1.5
package require ::tclapp::aldec::common::helpers 1.6

package provide ::tclapp::aldec::common::sim 1.5
package provide ::tclapp::aldec::common::sim 1.6

namespace eval ::tclapp::aldec::common {

Expand Down Expand Up @@ -327,6 +327,7 @@ proc usf_aldec_create_do_file_for_compilation { do_file } {
}

set vlog_arg_list [list]
::tclapp::aldec::common::helpers::usf_aldec_appendCompilationCoverageOptions vlog_arg_list vlog
if { [get_property [::tclapp::aldec::common::helpers::usf_aldec_getPropertyName COMPILE.DEBUG] $fs_obj] } {
lappend vlog_arg_list "-dbg"
}
Expand All @@ -341,6 +342,7 @@ proc usf_aldec_create_do_file_for_compilation { do_file } {
puts $fh "null \[set vlog_opts \{$vlog_cmd_str\}\]"

set vcom_arg_list [list]
::tclapp::aldec::common::helpers::usf_aldec_appendCompilationCoverageOptions vcom_arg_list vcom
if { [get_property [::tclapp::aldec::common::helpers::usf_aldec_getPropertyName COMPILE.VHDL_RELAX] $fs_obj] } {
lappend vcom_arg_list "-relax"
}
Expand Down Expand Up @@ -480,7 +482,9 @@ proc usf_aldec_get_simulation_cmdline {} {

set tool "asim"
set arg_list [list "$tool" "-t 1ps"]


::tclapp::aldec::common::helpers::usf_aldec_appendSimulationCoverageOptions arg_list

if { [get_property target_simulator [current_project]] == "ActiveHDL" } {
lappend arg_list "-asdb"
}
Expand Down
2 changes: 2 additions & 0 deletions tclapp/aldec/activehdl/common/tclIndex
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Expand Up @@ -6,6 +6,8 @@
# element name is the name of a command and the value is
# a script that loads the command.

set auto_index(::tclapp::aldec::common::helpers::usf_aldec_appendSimulationCoverageOptions) [list source [file join $dir helpers.tcl]]
set auto_index(::tclapp::aldec::common::helpers::usf_aldec_appendCompilationCoverageOptions) [list source [file join $dir helpers.tcl]]
set auto_index(::tclapp::aldec::common::helpers::usf_aldec_getSimulatorName) [list source [file join $dir helpers.tcl]]
set auto_index(::tclapp::aldec::common::helpers::usf_aldec_getLibraryPrefix) [list source [file join $dir helpers.tcl]]
set auto_index(::tclapp::aldec::common::helpers::usf_aldec_get_origin_dir_path) [list source [file join $dir helpers.tcl]]
Expand Down
2 changes: 1 addition & 1 deletion tclapp/aldec/activehdl/pkgIndex.tcl
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Expand Up @@ -8,4 +8,4 @@
# script is sourced, the variable $dir must contain the
# full path name of this file's directory.

package ifneeded ::tclapp::aldec::activehdl 1.5 [list source [file join $dir activehdl.tcl]]
package ifneeded ::tclapp::aldec::activehdl 1.6 [list source [file join $dir activehdl.tcl]]
26 changes: 25 additions & 1 deletion tclapp/aldec/activehdl/register_options.tcl
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Expand Up @@ -8,7 +8,7 @@

package require Vivado 1.2014.1

package require ::tclapp::aldec::common::helpers 1.5
package require ::tclapp::aldec::common::helpers 1.6

namespace eval ::tclapp::aldec::activehdl {
namespace export register_options
Expand Down Expand Up @@ -44,6 +44,20 @@ proc register_options { simulator } {
{{compile.vlog.more_options} {string} {} {More Verilog compilation options}}
{{compile.vcom.more_options} {string} {} {More VHDL compilation options}}

{{compile.statement_coverage} {bool} {0} {Statement Coverage}}
{{compile.branch_coverage} {bool} {0} {Branch Coverage}}
{{compile.expression_coverage} {bool} {0} {Expression Coverage}}
{{compile.condition_coverage} {bool} {0} {Condition Coverage}}
{{compile.path_coverage} {bool} {0} {Path Coverage}}
{{compile.assertion_coverage} {bool} {0} {Assertion Coverage}}
{{compile.fsm_coverage} {bool} {0} {FSM Coverage}}
{{compile.enable_expressions_on_subprogram_arguments} {bool} {0} {Enable expressions on subprogram arguments}}
{{compile.enable_atomic_expressions_in_the_conditional_statements} {bool} {0} {Enable atomic expressions in the conditional statements}}
{{compile.enable_the_expressions_consisting_of_one_variable_only} {bool} {0} {Enable the expressions consisting of one variable only}}
{{compile.enable_the_expressions_with_relational_operators} {bool} {0} {Enable the expressions with relational operators}}
{{compile.enable_the_expressions_returning_vectors} {bool} {0} {Enable the expressions returning vectors}}
{{compile.enable_fsm_sequences_in_fsm_coverage} {bool} {0} {Enable FSM sequences in FSM Coverage}}

{{elaborate.access} {bool} {0} {Enable access to objects optimized by default}}
{{elaborate.unifast} {bool} {0} {Enable fast simulation models}}

Expand All @@ -54,6 +68,16 @@ proc register_options { simulator } {
{{simulate.uut} {string} {} {Specify hierarchical path of unit under test instance}}
{{simulate.saif} {string} {} {Generate SAIF file for power analysis}}
{{simulate.asim.more_options} {string} {} {More simulation options}}

{{simulate.statement_coverage} {bool} {0} {Statement Coverage}}
{{simulate.branch_coverage} {bool} {0} {Branch Coverage}}
{{simulate.functional_coverage} {bool} {0} {Functional Coverage}}
{{simulate.expression_coverage} {bool} {0} {Expression Coverage}}
{{simulate.condition_coverage} {bool} {0} {Condition Coverage}}
{{simulate.path_coverage} {bool} {0} {Path Coverage}}
{{simulate.toggle_coverage} {bool} {0} {Toggle Coverage}}
{{simulate.assertion_coverage} {bool} {0} {Assertion Coverage}}
{{simulate.fsm_coverage} {bool} {0} {FSM Coverage}}
}
# create options
::tclapp::aldec::common::helpers::usf_create_options $simulator $options
Expand Down
2 changes: 1 addition & 1 deletion tclapp/aldec/activehdl/revision_history.txt
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@@ -1 +1 @@
1.5 Update 1.5: Separated compilation standard for SystemVerilog.
1.6 Update 1.6: Coverage options.
4 changes: 2 additions & 2 deletions tclapp/aldec/activehdl/sim.tcl
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Expand Up @@ -8,8 +8,8 @@

package require Vivado 1.2014.1

package require ::tclapp::aldec::common::sim 1.5
package require ::tclapp::aldec::common::helpers 1.5
package require ::tclapp::aldec::common::sim 1.6
package require ::tclapp::aldec::common::helpers 1.6

namespace eval ::tclapp::aldec::activehdl {

Expand Down
2 changes: 1 addition & 1 deletion tclapp/aldec/riviera/app.xml
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Expand Up @@ -2,7 +2,7 @@
<catalog>
<apps>
<app>
<revision_history>Update 1.5: Separated compilation standard for SystemVerilog.</revision_history>
<revision_history>Update 1.6: Coverage options.</revision_history>
<name>riviera</name>
<pkg_require>Vivado 2014.1</pkg_require>
<company>aldec</company>
Expand Down
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