Fix company name in 2017.2 branch for questa_cdc Tcl app

catalog/2017.3/aldec/activehdl/app.xml

@@ -2,7 +2,7 @@
 <catalog>
   <apps>
     <app>
-      <revision_history>Files grouped to speed up compilation. AXI-BFM settings updated. Pre/post tcl hooks added.</revision_history>
+      <revision_history>Generated scripts are now automatically made executable. List of libraries is now included in vlog command.</revision_history>
       <name>activehdl</name>
       <pkg_require>Vivado 2014.1</pkg_require>
       <company>aldec</company>

catalog/2017.3/aldec/activehdl/revision_history.txt

@@ -1,5 +1,7 @@
-1.10 Files grouped to speed up compilation. AXI-BFM settings updated. Pre/post tcl hooks added.
-1.9 export_simulation procedure and support for -lib_map_path switch added
-1.8 Fixed system file
-1.7 Update 1.7: Add mappings for libraries from compiled library location.
-1.6 Update 1.6: Coverage options.
+1.12 Generated scripts are now automatically made executable. List of libraries is now included in vlog command.
+1.11 Fixed bug with -scripts_only switch. Changed generated simulation script - now simulation works differently in batch mode. Removed fixed simulation resolution.
+1.10 Files grouped to speed up compilation. AXI-BFM settings updated. Pre/post tcl hooks added.
+1.9 export_simulation procedure and support for -lib_map_path switch added
+1.8 Fixed system file
+1.7 Update 1.7: Add mappings for libraries from compiled library location.
+1.6 Update 1.6: Coverage options.

catalog/2017.3/aldec/riviera/app.xml

@@ -2,7 +2,7 @@
 <catalog>
   <apps>
     <app>
-      <revision_history>Files grouped to speed up compilation. AXI-BFM settings updated. Pre/post tcl hooks added.</revision_history>
+      <revision_history>Generated scripts are now automatically made executable. List of libraries is now included in vlog command.</revision_history>
       <name>riviera</name>
       <pkg_require>Vivado 2014.1</pkg_require>
       <company>aldec</company>

catalog/2017.3/aldec/riviera/revision_history.txt

@@ -1,5 +1,7 @@
-1.10 Files grouped to speed up compilation. AXI-BFM settings updated. Pre/post tcl hooks added.
-1.9 export_simulation procedure and support for -lib_map_path switch added
-1.8 Fixed system file
-1.7 Update 1.7: Add mappings for libraries from compiled library location.
-1.6 Update 1.6: Coverage options.
+1.12 Generated scripts are now automatically made executable. List of libraries is now included in vlog command.
+1.11 Fixed bug with -scripts_only switch. Changed generated simulation script - now simulation works differently in batch mode. Removed fixed simulation resolution.
+1.10 Files grouped to speed up compilation. AXI-BFM settings updated. Pre/post tcl hooks added.
+1.9 export_simulation procedure and support for -lib_map_path switch added
+1.8 Fixed system file
+1.7 Update 1.7: Add mappings for libraries from compiled library location.
+1.6 Update 1.6: Coverage options.

catalog/2017.3/bluepearl/bpsvvs/app.xml

@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="utf-8"?>
+<catalog>
+  <apps>
+    <app>
+      <revision_history>Fix for missing global includes. Fix for black boxed IP</revision_history>
+      <name>bpsvvs</name>
+      <pkg_require>Vivado 2014.1</pkg_require>
+      <company>bluepearl</company>
+      <company_display>Blue Pearl Software, Inc.</company_display>
+      <summary>This is a Blue Pearl Software Visual Verification Suite (VVS) integration app that helps you load your Xilinx design into Blue Pearl&apos;s Visual Verification Suite RTL debugging environment.</summary>
+      <display>Blue Pearl Visual Verification Suite</display>
+      <procs>
+        <proc>
+          <name>generate_bps_project</name>
+          <summary>Generates the Blue Pearl Tcl project file</summary>
+        </proc>
+        <proc>
+          <name>launch_bps</name>
+          <summary>Launches Blue Pearl Visual Verification Suite</summary>
+        </proc>
+        <proc>
+          <name>update_vivado_into_bps</name>
+          <summary>Updates the current results into the Blue Pearl Visual Verification Suite</summary>
+        </proc>
+      </procs>
+    </app>
+  </apps>
+</catalog>

catalog/2017.3/bluepearl/bpsvvs/revision_history.txt

@@ -0,0 +1,2 @@
+1.1 Fix for missing global includes. Fix for black boxed IP
+1.0 Initial Revision

catalog/2017.3/icl/protoip/app.xml

@@ -2,7 +2,7 @@
 <catalog>
   <apps>
     <app>
-      <revision_history>Added possibility of SoC prototyping (CPU and FPGA)</revision_history>
+      <revision_history>Fixed bugs and improved SoC flow</revision_history>
       <name>protoip</name>
       <pkg_require>Vivado 2015.1</pkg_require>
       <author>Bulat Khusainov</author>

catalog/2017.3/icl/protoip/revision_history.txt

@@ -1 +1,2 @@
-2.0 Added possibility of SoC prototyping (CPU and FPGA)
+2.1 Fixed bugs and improved SoC flow
+2.0 Fixed bugs and improved SoC prototyping flow

catalog/2017.3/mentor/questa_cdc/app.xml

@@ -2,7 +2,7 @@
 <catalog>
   <apps>
     <app>
-      <revision_history>Initial version</revision_history>
+      <revision_history>support to add button in Vivado UI for Questa CDC</revision_history>
       <name>questa_cdc</name>
       <company>mentor</company>
       <company_display>Mentor Graphics, Inc.</company_display>

catalog/2017.3/mentor/questa_cdc/revision_history.txt

@@ -1 +1,2 @@
+1.1 support to add button in Vivado UI for Questa CDC
 1.0 Initial version

catalog/2017.3/mycompany/template/app.xml

@@ -8,7 +8,8 @@
       <procs>
         <proc>
           <name>my_command1</name>
-          <summary>Multi-lines summary of &#10;what the proc is doing</summary>
+          <summary>Multi-lines summary of 
+what the proc is doing</summary>
         </proc>
         <proc>
           <name>my_command2</name>

catalog/2017.3/xilinx/designutils/app.xml

@@ -2,7 +2,7 @@
 <catalog>
   <apps>
     <app>
-      <revision_history>Added support for UltraScale Plus (get_sll_nets, get_sll_nodes)</revision_history>
+      <revision_history>Updated insert_buffer.tcl to better support UltraScale/UltraScale Plus. Minor update to prettyTable.</revision_history>
       <name>designutils</name>
       <pkg_require>Vivado 2014.1</pkg_require>
       <company>xilinx</company>
@@ -116,7 +116,10 @@
         </proc>
         <proc>
           <name>reapply_iostandard</name>
-          <summary>This command queries the tool-chosen defaults from implementation &#10;and &quot;apply&quot; them so it looks like the user did it from the beginning. &#10;This complies with the bit export restriction that all ios be LOCd and &#10;explicitly set to an IO Standard</summary>
+          <summary>This command queries the tool-chosen defaults from implementation 
+and &quot;apply&quot; them so it looks like the user did it from the beginning. 
+This complies with the bit export restriction that all ios be LOCd and 
+explicitly set to an IO Standard</summary>
         </proc>
         <proc>
           <name>remove_buffer</name>

catalog/2017.3/xilinx/designutils/revision_history.txt

@@ -1,3 +1,4 @@
+1.31 Updated insert_buffer.tcl to better support UltraScale/UltraScale Plus. Minor update to prettyTable.
 1.30 Added support for UltraScale Plus (get_sll_nets, get_sll_nodes)
 1.29 Various enhancements to prettyTable
 1.28 Miscellaneous enhancements (timing_report_to_verilog, convert_muxfx_to_luts, create_combined_mig_io_design)

catalog/2017.3/xilinx/diff/app.xml

@@ -11,7 +11,9 @@
       <procs>
         <proc>
           <name>activate_design</name>
-          <summary>Activates (makes active) the project and design of the number specified, &#10;options are 1 or 2.  The project and design are set via set_compare_objects &#10;(or open_checkpoints).</summary>
+          <summary>Activates (makes active) the project and design of the number specified, 
+options are 1 or 2.  The project and design are set via set_compare_objects 
+(or open_checkpoints).</summary>
         </proc>
         <proc>
           <name>assert_fail</name>
@@ -51,15 +53,24 @@
         </proc>
         <proc>
           <name>compare_designs</name>
-          <summary>References the design/project combinations set with set_compare_objects. Then a &apos;design_command&apos; &#10;is executed with each design being made active and the outputs of those commands are captured. &#10;Those outputs are then compared using the specified &apos;difference_command&apos;. The design/project &#10;values must have been set with set_compare_objects (or open_checkpoints) before executing this command. &#10; &#10;e.g. &#10;open_checkpoints design1.dcp design2.dcp; # calls set_compare_objects for us and opens the DCPs &#10;compare_designs compare_lines { report_timing -return_string -max_paths 1000 }</summary>
+          <summary>References the design/project combinations set with set_compare_objects. Then a &apos;design_command&apos; 
+is executed with each design being made active and the outputs of those commands are captured. 
+Those outputs are then compared using the specified &apos;difference_command&apos;. The design/project 
+values must have been set with set_compare_objects (or open_checkpoints) before executing this command. 
+
+e.g. 
+open_checkpoints design1.dcp design2.dcp; # calls set_compare_objects for us and opens the DCPs 
+compare_designs compare_lines { report_timing -return_string -max_paths 1000 }</summary>
         </proc>
         <proc>
           <name>compare_dirs</name>
           <summary>Compares directory contents.</summary>
         </proc>
         <proc>
           <name>compare_files</name>
-          <summary>Compares file contents. Similar to the linux diff command. This algorithm is designed to be fast and &#10;does not find the best matches between files. For best matching use linux diff or the compare_lines_lcs &#10;command, but be aware: the compare_lines_lcs has a long runtime.</summary>
+          <summary>Compares file contents. Similar to the linux diff command. This algorithm is designed to be fast and 
+does not find the best matches between files. For best matching use linux diff or the compare_lines_lcs 
+command, but be aware: the compare_lines_lcs has a long runtime.</summary>
         </proc>
         <proc>
           <name>compare_lines</name>
@@ -75,7 +86,8 @@
         </proc>
         <proc>
           <name>compare_serialized_objects</name>
-          <summary>Compare serialized object properties. To serialize objects use the command serialize_objects. &#10;To read in objects that have been serialized to disk use serialize_from_file.</summary>
+          <summary>Compare serialized object properties. To serialize objects use the command serialize_objects. 
+To read in objects that have been serialized to disk use serialize_from_file.</summary>
         </proc>
         <proc>
           <name>compare_unordered_lists</name>
@@ -91,19 +103,27 @@
         </proc>
         <proc>
           <name>get_global_report</name>
-          <summary>Gets global report value. The output of this command is what resource will be used to output data &#10;if unique resources are not provided to the print_* commands.  Use set_global_report to change.</summary>
+          <summary>Gets global report value. The output of this command is what resource will be used to output data 
+if unique resources are not provided to the print_* commands.  Use set_global_report to change.</summary>
         </proc>
         <proc>
           <name>get_verbose</name>
           <summary>Gets verbosity mode.</summary>
         </proc>
         <proc>
           <name>html_escape</name>
-          <summary>Escapes all XML characters. &#10;&amp; = &amp;amp; &#10;&quot; = &amp;quot; &#10;&apos; = &amp;apos; &#10;&lt; = &amp;lt; &#10;&gt; = &amp;gt;</summary>
+          <summary>Escapes all XML characters. 
+&amp; = &amp;amp; 
+&quot; = &amp;quot; 
+&apos; = &amp;apos; 
+&lt; = &amp;lt; 
+&gt; = &amp;gt;</summary>
         </proc>
         <proc>
           <name>open_checkpoints</name>
-          <summary>Opens checkpoints while capturing the corresponding design and project objects. &#10;Channel is not specified here, and cannot be used with the design comparison flow. &#10;Use the set_global_report for controlling the outputs channel with design comparisons.</summary>
+          <summary>Opens checkpoints while capturing the corresponding design and project objects. 
+Channel is not specified here, and cannot be used with the design comparison flow. 
+Use the set_global_report for controlling the outputs channel with design comparisons.</summary>
         </proc>
         <proc>
           <name>print_alert</name>
@@ -191,15 +211,18 @@
         </proc>
         <proc>
           <name>set_global_report</name>
-          <summary>Sets global report file name and can be set to stdout or stderr. If not specified, then each &#10;print_* command requires a file name be provided to the channel argument. If the file name &#10;has the extension &apos;htm&apos; or &apos;html&apos;, then an HTML report will be generated.</summary>
+          <summary>Sets global report file name and can be set to stdout or stderr. If not specified, then each 
+print_* command requires a file name be provided to the channel argument. If the file name 
+has the extension &apos;htm&apos; or &apos;html&apos;, then an HTML report will be generated.</summary>
         </proc>
         <proc>
           <name>set_verbose</name>
           <summary>Sets verbosity mode. True or 1 will print verbose, false or 0 will not.</summary>
         </proc>
         <proc>
           <name>unique_in_both_sets</name>
-          <summary>Find the unique items in set1 and in set2. Also known as the &apos;Symmetric Difference&apos; or &#10;(A\B) U (B\A) [ ( $set1 \ $set2 ) U ( $set2 \ $set1 ) ].</summary>
+          <summary>Find the unique items in set1 and in set2. Also known as the &apos;Symmetric Difference&apos; or 
+(A\B) U (B\A) [ ( $set1 \ $set2 ) U ( $set2 \ $set1 ) ].</summary>
         </proc>
         <proc>
           <name>unique_in_first_set</name>

catalog/2017.3/xilinx/ies/app.xml

@@ -2,7 +2,7 @@
 <catalog>
   <apps>
     <app>
-      <revision_history>extract xml comp files for finding SV pkg libraries</revision_history>
+      <revision_history>reference xilinx_vip include directory for ovm/uvm based designs</revision_history>
       <name>ies</name>
       <pkg_require>Vivado 2014.1</pkg_require>
       <company>xilinx</company>

catalog/2017.3/xilinx/ies/revision_history.txt

@@ -1,3 +1,20 @@
+3.58 reference xilinx_vip include directory for ovm/uvm based designs
+3.57 fetch requires_vip property on the fetched IP object
+3.56 reference xilinx_vip if requires_vip property is set on the IP instance
+3.55 reference xilinx_vip if requires_vip property is set on the IP
+3.54 initial support for systemC source compilation
+3.53 support for systemC source compilation
+3.52 compile glbl if XPM_CDC core is being referenced in the design
+3.51 additionally reference precompiled AXI-VIP library if param is set
+3.50 reference precompiled AXI-VIP library if param is set
+3.49 reference precompiled AXI-VIP library
+3.48 use global incremental property on simulation fileset
+3.47 add software build info in script header
+3.46 compile files into simulator library dir with _lib suffix
+3.45 add copyright version header in script files
+3.44 reference user specified XPM data if param set
+3.43 refactored procs into utils
+3.42 check for empty source file object before extracting
 3.41 extract xml comp files for finding SV pkg libraries
 3.40 source user tcl file from wrapper generated in run directory
 3.39 fetch sv files in quiet mode as those may not be part of compile order