A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals.

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

the implementation of the ASAD_DenseNet

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

📖 北京理工大学非官方 LaTeX 模板集合，包含本科、研究生毕业设计模板及更多。🎉 （更多文档请访问 wiki 和 release 中的手册）

Deep Learning Accelerator (Convolution Neural Networks)

Reconfigurable implementation and evaluation of the Bit Pragmatic Deep Learning Inference engine

A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network

Convolutional accelerator kernel, target ASIC & FPGA

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

AXI interface modules for Cocotb

Common SystemVerilog components

SystemVerilog modules and classes commonly used for verification

CNN acceleration on virtex-7 FPGA with verilog HDL

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

4 stage, in-order, compute RISC-V core based on the CV32E40P

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

A scalable Eyeriss model in SystemC.

A framework for fast exploration of the depth-first scheduling space for DNN accelerators

DRM Watch 3 - Наручний годинник з дисплеєм SHARP Memory LCD

The Ultra-Low Power RISC-V Core

A Verilog implementation of a CNN accelerator.

POSSUMM - PCA of Sparse, SUper Massive Matrices

ES-203 Computer Organization & Architecture CNN on FPGA board

🍀 Tensorflow implementation of various Attention Mechanisms, MLP, Re-parameter, Convolution, which is helpful to further understand papers.⭐⭐⭐