Semiconductor engineering and AI hardware company specializing in ASIC design, verification, FPGA prototyping, and intelligent energy optimization systems.

Yarok-14 Technologies builds intelligent hardware–software systems that unite silicon, data, and real-world impact. Founded by Bibin N. Biji, we deliver timing-aware ASIC/SoC design, FPGA bring-up,…

High-Performance Parameterized Systolic Array Accelerator Production-Grade RTL Design & Verification Environment

Comprehensive solution for monitoring and control of biomethane production, optimizing financial feasibility, and reducing process retention time.

Parameterized 256KB L2 Cache Controller — SystemVerilog RTL, MESI Coherency, AXI4/ACE, UVM-1.2 Testbench, JasperGold FPV, DFT Scan/BIST, Synopsys DC Synthesis, Cadence Innovus P&R

Behavioral-to-architectural RTL model of a GPU-style SerDes subsystem

This project implements a behaviorally realistic PCIe Endpoint driven by an AXI-Lite interface, verified using coverage-driven UVM, strengthened with SystemVerilog Assertions (SVA) and Formal Verif…

A methodology-driven study and automation framework for comparing clock distribution architectures with a focus on skew, latency, and dynamic power.

16-bit Pipelined RISC Processor (RTL → GDSII): Executed full DC-ICC2-PrimeTime-Calibre flow; achieved WNS +0.03 ns, TNS 0; completed CTS, MCMM STA, IR/EM, and DRC/LVS sign-off using fully automated…

Automated Front-End VLSI Design tool. Uses an LLM-RAG pipeline to transform high-level design specifications into PPA-optimized, synthesizable RTL IP blocks (Verilog/VHDL). Features an iterative ve…

Cadence Innovus | Timing Closure @ 500 MHz | Signoff Clean

Industry standard RTL IP blocks for front-end VLSI design. Includes synthesizable, reusable, parameterized modules with lint-clean coding (Verible/Spyglass). Fully testbench-validated using Icarus/…

This repository contains a production‑ready, synthesizable USB 3.2 Host/Device Link‑Layer IP with Design‑for‑Test (DFT) features and verification collateral.

𝗙𝗿𝗼𝗺 𝗧𝗿𝗮𝗻𝘀𝗳𝗼𝗿𝗺𝗲𝗿𝘀 𝘁𝗼 𝗥𝗲𝗮𝘀𝗼𝗻𝗶𝗻𝗴 𝗟𝗟𝗠𝘀: 𝟭𝟱 𝗣𝗮𝗽𝗲𝗿𝘀 𝗧𝗵𝗮𝘁 𝗦𝗵𝗮𝗽𝗲𝗱 𝗠𝗼𝗱𝗲𝗿𝗻 𝗔𝗜

FlitZip is a Verilog-based hardware compression and decompression design for efficient data transmission. It uses comparator logic, priority encoding, and bit manipulation to reduce data width, sui…

This repository is a structured learning and reference resource for Formal Verification using Synopsys VC Formal. It covers core concepts, real applications, setup guides, reports, and project arti…

This project focuses on the design and implementation of I²C (Inter-Integrated Circuit) and SPI (Serial Peripheral Interface) communication protocols using Verilog HDL. The objective is to develop …

Verilog RTL implementation of a packet-switched Network-on-Chip with input buffering, virtual channel allocation, switch allocation, and crossbar-based routing.

A curated catalogue of high-quality Computer Architecture, Computer Systems, and Computer Engineering resources. This repository organizes links to courses, papers, tools, tutorials, communities, a…

End-to-end LLM pipeline: QLoRA finetuning (1B–7B), LoRA merge, GPTQ/AWQ quantization, FastAPI + vLLM inference server, GPU-ready Docker deployment, VRAM calculator, and a clean, production-grade mo…

Designed and developed a full-featured job application system with secure OTP-based applicant verification, an employer-only dashboard, and Dockerized deployment. Built using Python Flask with fro…

Here is the complete GitHub README, summarizing your DDR2 SDRAM Memory Controller project, including design files, testbench requirements, and simulation instructions. 🚀 DDR2 SDRAM Memory Controlle…