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area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMICLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIgood first issueIssue should be easy to implement, good for first-time contributorsIssue should be easy to implement, good for first-time contributorshelp wanted[up-for-grabs] Good issue for external contributors[up-for-grabs] Good issue for external contributorstenet-performancePerformance related issuePerformance related issue
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A good first issue for those who are interested in SIMD and ARM64. Should improve #63285
bool IsZero(Vector128<byte> v) => v == Vector128<byte>.Zero;Currently is suboptimal on ARM64:

while I'd expect it to emit something like this:

so if one of the args of == is _Zero it needs to use umaxv, it should be done here:
runtime/src/coreclr/jit/lowerarmarch.cpp
Line 864 in 386f871
| comp->gtNewSimdHWIntrinsicNode(simdType, cmp, NI_AdvSimd_Arm64_MinAcross, CORINFO_TYPE_UBYTE, simdSize); |
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area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMICLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIgood first issueIssue should be easy to implement, good for first-time contributorsIssue should be easy to implement, good for first-time contributorshelp wanted[up-for-grabs] Good issue for external contributors[up-for-grabs] Good issue for external contributorstenet-performancePerformance related issuePerformance related issue