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Arm64/Sve: Predicated Abs, Predicated/UnPredicated Add, Conditional Select #100743

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Merged
kunalspathak merged 52 commits into from
Apr 24, 2024
Merged

Arm64/Sve: Predicated Abs, Predicated/UnPredicated Add, Conditional Select #100743

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0d437e3
JIT ARM64-SVE: Add Sve.Abs() and Sve.Add()
a74nh Mar 11, 2024
e9fa735
Fix sve scaling in enitIns_R_S/S_R
a74nh Mar 22, 2024
5acc122
Revert "Fix sve scaling in enitIns_R_S/S_R"
a74nh Mar 23, 2024
15e893d
Fix sve scaling in enitIns_R_S/S_R
a74nh Mar 23, 2024
c22f458
Restore testing
a74nh Mar 24, 2024
508a52a
Use NaturalScale_helper for vector load/stores
a74nh Mar 25, 2024
5825c20
Merge remote-tracking branch 'origin/main' into api_abs_github
kunalspathak Mar 28, 2024
9081fa3
Merge remote-tracking branch 'origin/main' into api_abs_github
kunalspathak Apr 3, 2024
d4f3c86
wip
kunalspathak Apr 3, 2024
20defbd
Add ConditionalSelect() APIs
kunalspathak Apr 4, 2024
c70367f
Handle ConditionalSelect in JIT
kunalspathak Apr 4, 2024
1896b21
Add test coverage
kunalspathak Apr 4, 2024
2e0d022
Update the test cases
kunalspathak Apr 6, 2024
185fcfa
jit format
kunalspathak Apr 6, 2024
88e8f87
Merge branch 'sve-conditional-select' into abi_abs_conditional
kunalspathak Apr 6, 2024
ebcb174
fix merge conflicts
kunalspathak Apr 6, 2024
28aa7b7
Make predicated/unpredicated work with ConditionalSelect
kunalspathak Apr 7, 2024
1c7b4b2
Misc. changes
kunalspathak Apr 7, 2024
6adf6c6
jit format
kunalspathak Apr 7, 2024
ecf4e01
jit format
kunalspathak Apr 7, 2024
c6fef82
Merge remote-tracking branch 'origin/main' into abi_abs_conditional
kunalspathak Apr 7, 2024
d780156
Handle all the conditions correctly
kunalspathak Apr 8, 2024
eb4d1dc
jit format
kunalspathak Apr 9, 2024
00aacab
fix some spacing
kunalspathak Apr 9, 2024
f716958
Removed the assert
kunalspathak Apr 9, 2024
5eadcf9
fix the largest vector size to 64 to fix #100366
kunalspathak Apr 9, 2024
bc6e58d
review feedback
kunalspathak Apr 11, 2024
19ec4b6
wip
kunalspathak Apr 11, 2024
ed7c781
Add SVE feature detection for Windows
kunalspathak Apr 11, 2024
f966b5e
fix the check for invalid alignment
kunalspathak Apr 11, 2024
f0c81f1
Revert "Add SVE feature detection for Windows"
kunalspathak Apr 11, 2024
89ede7d
Handle case where Abs() is wrapped in another conditionalSelect
kunalspathak Apr 11, 2024
1f44b2f
jit format
kunalspathak Apr 12, 2024
9712a16
fix the size comparison
kunalspathak Apr 12, 2024
0ad2e64
HW_Flag_MaskedPredicatedOnlyOperation
kunalspathak Apr 12, 2024
f76e324
Revert the change in emitarm64.cpp around INS_sve_ldr_mask/INS_sve_st…
kunalspathak Apr 12, 2024
8af7108
Fix the condition for lowering
kunalspathak Apr 14, 2024
e934e26
address review feedback for movprfx
kunalspathak Apr 22, 2024
0daeac7
Move the special handling of Vector<>.Zero from lowerer to importer
kunalspathak Apr 22, 2024
635a7d7
Rename IsEmbeddedMaskedOperation/IsOptionalEmbeddedMaskedOperation
kunalspathak Apr 22, 2024
19da982
Add more test coverage for conditionalSelect
kunalspathak Apr 22, 2024
f1b8b17
Rename test method name
kunalspathak Apr 23, 2024
409a039
Add more test coverage for conditionalSelect:Abs
kunalspathak Apr 23, 2024
0c8a14d
jit format
kunalspathak Apr 23, 2024
53c5eb3
Add logging on test methods
kunalspathak Apr 23, 2024
868229f
Merge remote-tracking branch 'origin/main' into abi_abs_conditional
kunalspathak Apr 23, 2024
9ae3c78
Add the missing movprfx for abs
kunalspathak Apr 23, 2024
c8244eb
Add few more scenarios where falseVal is zero
kunalspathak Apr 23, 2024
f6eb1fe
Make sure LoadVector is marked as explicit needing mask
kunalspathak Apr 23, 2024
83e1b1b
revisit the codegen logic
kunalspathak Apr 24, 2024
c78e0c7
Remove commented code and add some other comments
kunalspathak Apr 24, 2024
6aa2386
jit format
kunalspathak Apr 24, 2024
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Use NaturalScale_helper for vector load/stores
  • Loading branch information
@a74nh
a74nh committed Mar 25, 2024
commit 508a52a23245d1b49bb65882d1a6e43341c16a42
4 changes: 2 additions & 2 deletions src/coreclr/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9836,7 +9836,7 @@ void emitter::emitIns_R_S(instruction ins, emitAttr attr, regNumber reg1, int va
fmt = IF_SVE_IE_2A;

// TODO-SVE: Don't assume 128bit vectors
scale = 4;
scale = NaturalScale_helper(EA_16BYTE);
ssize_t mask = (1 << scale) - 1; // the mask of low bits that must be zero to encode the immediate

if (((imm & mask) == 0) && (isValidSimm<9>(imm >> scale)))
Expand Down Expand Up @@ -10115,7 +10115,7 @@ void emitter::emitIns_S_R(instruction ins, emitAttr attr, regNumber reg1, int va
fmt = IF_SVE_JH_2A;

// TODO-SVE: Don't assume 128bit vectors
scale = 4;
scale = NaturalScale_helper(EA_16BYTE);
ssize_t mask = (1 << scale) - 1; // the mask of low bits that must be zero to encode the immediate

if (((imm & mask) == 0) && (isValidSimm<9>(imm >> scale)))
Expand Down