[RISC-V] Enable instruction printing for `PHASE Generate code` in JIT dump #122485

SkyShield · 2025-12-12T09:15:26Z

RISC-V instructions were not printed during PHASE Generate code, which made debugging inconvenient.

This PR enables printing RISC-V instructions when JitDump is set:

Before (`PHASE Generate code`):

Generating: N085 (  1,  1) [000039] -----------                   t39 =    LCL_VAR   double V03 loc3         u:2 fs6 REG fs6 $2c1
                                                                        /--*  t39    double 
Generating: N087 (  2,  2) [000040] -----------                   t40 = *  NEG       double REG fa0 $182
                                                                        /--*  t40    double 
Generating: N089 (???,???) [000134] -----------                  t134 = *  PUTARG_REG double REG fa0
                                                                        /--*  t134   double arg0 fa0
Generating: N091 ( 16,  5) [000123] --C-G-----Z                  t123 = *  CALL      double System.Math:Exp(double):double REG fa0
Call: GCvars=0000000000000000 {}, gcrefRegs=C0000 {s2 s3}, byrefRegs=0000 {}

After (`PHASE Generate code`):

Generating: N085 (  1,  1) [000039] -----------                   t39 =    LCL_VAR   double V03 loc3         u:2 fs6 REG fs6 $2c1
                                                                        /--*  t39    double 
Generating: N087 (  2,  2) [000040] -----------                   t40 = *  NEG       double REG fa0 $182
            fneg.d         fa0, fs6
                                                                        /--*  t40    double 
Generating: N089 (???,???) [000134] -----------                  t134 = *  PUTARG_REG double REG fa0
                                                                        /--*  t134   double arg0 fa0
Generating: N091 ( 16,  5) [000123] --C-G-----Z                  t123 = *  CALL      double System.Math:Exp(double):double REG fa0
Call: GCvars=0000000000000000 {}, gcrefRegs=C0000 {s2 s3}, byrefRegs=0000 {}
            auipc          ra, ??
            jalr           ra, ??(ra)		// System.Math:Exp(double):double

Limitation

In the current RISC-V implementation, it's difficult to compute the actual jump offset during CodeGen. Thus, a placeholder "??" is printed instead.

@clamp03 @tomeksowi @namu-lee @credo-quia-absurdum
part of #84834, cc @dotnet/samsung

… for debugging

…ging

SkyShield · 2025-12-12T09:58:22Z

@dotnet-policy-service agree

tomeksowi

Can you run some asmdiffs to make sure these changes don't affect the actual codegen?

tomeksowi · 2025-12-17T15:34:16Z

src/coreclr/jit/emitriscv64.cpp

+                if ((addr == nullptr) && (offset == 0))
+                {
+                    // If address is not given, print placeholder instead.
+                    printf("??");
+                }
+                else
+                {
+                    emitDispImmediate(offset, false);
+                }


Branches without a label may need similar treatment.

Handled non-labeled branch offsets in emitDispBranchOffset. Thanks.

SkyShield · 2025-12-17T16:19:10Z

No differences were found when compared with feea419.

Diffs are based on 87,412 contexts (85,743 MinOpts, 1,669 FullOpts).

Overall (+0 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
System.mch	32,089,346	+0	0.00%

MinOpts (+0 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
System.mch	31,407,428	+0	0.00%

FullOpts (+0 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
System.mch	681,918	+0	0.00%

Example diffs

System.mch

+0 (0.00%) : 29.dasm - System.Diagnostics.Tracing.EventSource:InitializeDefaultEventSources() (FullOpts)

No diffs found?

+0 (0.00%) : 33.dasm - System.AppContext:TryGetSwitch(System.String,byref):bool (FullOpts)

No diffs found?

+0 (0.00%) : 109.dasm - System.RuntimeType+RuntimeTypeCache+MemberInfoCache`1[System.__Canon]:Populate(System.String,int,int):System.__Canon[]:this (FullOpts)

No diffs found?

+0 (0.00%) : 87356.dasm - System.Net.Http.HPack.HPackEncoder:EncodeLiteralHeaderFieldWithoutIndexingNewNameToAllocatedArray(System.String):byte[] (MinOpts)

No diffs found?

+0 (0.00%) : 87352.dasm - System.Net.Http.HPack.HPackEncoder:EncodeValueStringPart(System.String,System.Span`1[byte]) (MinOpts)

No diffs found?

+0 (0.00%) : 87348.dasm - System.Net.Http.HPack.HPackEncoder:EncodeLiteralHeaderFieldWithoutIndexing(int,System.Span`1[byte],byref):bool (MinOpts)

No diffs found?

Details

Size improvements/regressions per collection

Collection	Contexts with diffs	Improvements	Regressions	Same size	Improvements (bytes)	Regressions (bytes)
System.mch	2,713	0	0	2,713	-0	+0

PerfScore improvements/regressions per collection

Collection	Contexts with diffs	Improvements	Regressions	Same PerfScore	Improvements (PerfScore)	Regressions (PerfScore)	PerfScore Overall in FullOpts
System.mch	2,713	0	0	2,713	0.00%	0.00%	0.0000%

Context information

Collection	Diffed contexts	MinOpts	FullOpts	Missed, base	Missed, diff
System.mch	87,412	85,743	1,669	0 (0.00%)	0 (0.00%)

jit-analyze output

SkyShield · 2025-12-18T06:09:35Z

After the change, asmdiffs showed no differences compared to 13ee790.

Diffs are based on 87,627 contexts (85,970 MinOpts, 1,657 FullOpts).

Overall (+0 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
System.mch	32,167,222	+0	0.00%

MinOpts (+0 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
System.mch	31,487,584	+0	0.00%

FullOpts (+0 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
System.mch	679,638	+0	0.00%

Example diffs

System.mch

+0 (0.00%) : 1409.dasm - System.Diagnostics.Process:GetNextArgument(System.String,byref):System.String (MinOpts)

No diffs found?

+0 (0.00%) : 1985.dasm - System.ModuleHandle:ResolveTypeHandle(int,System.RuntimeTypeHandle[],System.RuntimeTypeHandle[]):System.RuntimeTypeHandle:this (FullOpts)

No diffs found?

+0 (0.00%) : 3841.dasm - System.Timers.Timer:.ctor():this (MinOpts)

No diffs found?

+0 (0.00%) : 79424.dasm - System.Threading.RateLimiting.DefaultPartitionedRateLimiter`2+d__20[System.__Canon,long]:MoveNext():this (MinOpts)

No diffs found?

+0 (0.00%) : 78464.dasm - System.Net.Security.SslApplicationProtocol:.cctor() (MinOpts)

No diffs found?

+0 (0.00%) : 77568.dasm - System.Text.Encodings.Web.OptimizedInboxTextEncoder+AsciiPreescapedData:PopulatePreescapedData(byref,System.Text.Encodings.Web.ScalarEscaperBase):this (MinOpts)

No diffs found?

Details

Size improvements/regressions per collection

Collection	Contexts with diffs	Improvements	Regressions	Same size	Improvements (bytes)	Regressions (bytes)
System.mch	2,720	0	0	2,720	-0	+0

PerfScore improvements/regressions per collection

Collection	Contexts with diffs	Improvements	Regressions	Same PerfScore	Improvements (PerfScore)	Regressions (PerfScore)	PerfScore Overall in FullOpts
System.mch	2,720	0	0	2,720	0.00%	0.00%	0.0000%

Context information

Collection	Diffed contexts	MinOpts	FullOpts	Missed, base	Missed, diff
System.mch	87,627	85,970	1,657	0 (0.00%)	0 (0.00%)

jit-analyze output

SkyShield added 17 commits November 25, 2025 13:53

Fix typo emitDisInsName -> emitDispInsName

c48ad10

[RISC-V] Fix typo Ldsp -> LdSp

fc99edb

[RISC-V] Enable emitter::dispIns to print readable assemblies

fbf5811

[RISC-V] Emit instrDescLoadImm and instrDesc in 'generate code phase'…

778f97f

… for debugging

[RISC-V] Print jalr instructions in generate code phase for debug…

35ad002

…ging

[RISC-V] Initial implementation of emitDispIns

a9d7321

[RISC-V] Make emitDispIns has similar sturcture with emitOutputInstr

42c752e

[RISC-V] Split logics into different functions

7cfd98b

[RISC-V] Factor out similar logics and pack into policies

93c83ca

[RISC-V] Comments, chores

e5941cb

[RISC-V] Print placeholder "??" while formatting

c9f6850

[RISC-V] Trim trailing whitespaces

eb1bda5

[RISC-V] Add a comment with an example of jump offset optimization

561e6f5

[RISC-V] Formatting

4b0c7e9

Merge main

43442b5

[RISC-V] Remove assertion

07498fa

[RISC-V] Format & change EmitLogic_Opts... to non-static

14c2c4c

github-actions bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Dec 12, 2025

dotnet-policy-service bot added the community-contribution Indicates that the PR has been added by a community member label Dec 12, 2025

clamp03 assigned SkyShield Dec 12, 2025

clamp03 added the arch-riscv Related to the RISC-V architecture label Dec 12, 2025

clamp03 requested a review from tomeksowi December 12, 2025 09:57

SkyShield changed the title ~~[RISC-V] Enable instruction print for PHASE Generate code of JIT dump~~ [RISC-V] Enable instruction printing for PHASE Generate code in JIT dump Dec 12, 2025

tomeksowi reviewed Dec 17, 2025

View reviewed changes

SkyShield added 2 commits December 18, 2025 14:32

[RISC-V] Print placeholder while formatting branch offset

13a286f

[RISC-V] Code formatting

d1b9b0d

[RISC-V] Align the message with normal cases

c64e614

tomeksowi approved these changes Dec 18, 2025

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[RISC-V] Enable instruction printing for `PHASE Generate code` in JIT dump #122485

[RISC-V] Enable instruction printing for `PHASE Generate code` in JIT dump #122485

SkyShield commented Dec 12, 2025 •

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SkyShield Dec 18, 2025 •

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SkyShield commented Dec 17, 2025

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jit-analyze output

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SkyShield commented Dec 18, 2025 •

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[RISC-V] Enable instruction printing for PHASE Generate code in JIT dump #122485

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[RISC-V] Enable instruction printing for PHASE Generate code in JIT dump #122485

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SkyShield commented Dec 12, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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Before (PHASE Generate code):

After (PHASE Generate code):

Limitation

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SkyShield commented Dec 12, 2025

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SkyShield Dec 18, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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SkyShield commented Dec 17, 2025

Size improvements/regressions per collection

PerfScore improvements/regressions per collection

Context information

jit-analyze output

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SkyShield commented Dec 18, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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Size improvements/regressions per collection

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jit-analyze output

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[RISC-V] Enable instruction printing for `PHASE Generate code` in JIT dump #122485

[RISC-V] Enable instruction printing for `PHASE Generate code` in JIT dump #122485

SkyShield commented Dec 12, 2025 •

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Before (`PHASE Generate code`):

After (`PHASE Generate code`):

SkyShield Dec 18, 2025 •

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SkyShield commented Dec 18, 2025 •

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