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[Arm64] Implement Store Hardware Intrinsic #33535

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Merged
echesakov merged 12 commits into from
Mar 19, 2020
Merged

[Arm64] Implement Store Hardware Intrinsic #33535

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80c7ad8
Put FusedMultiplyAdd and FusedMultiplySubtract after Divide in AdvSim…
echesakov Mar 11, 2020
9b61408
Add Store in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
echesakov Mar 11, 2020
0d56a72
Add Store in hwintrinsiclistarm64.h
echesakov Mar 11, 2020
09580d0
Add Store in CodeGen::genHWIntrinsic() in hwintrinsiccodegenarm64.cpp
echesakov Mar 12, 2020
feed1b7
lookupSimdSize for Category_MemoryStore should return second argument…
echesakov Mar 12, 2020
cb4ffdd
Update System.Runtime.Intrinsics.Experimental.cs
echesakov Mar 11, 2020
d1afc1e
Add StoreUnOpTest.template
echesakov Mar 11, 2020
3e1ec01
Add Store in GenerateTests.csx
echesakov Mar 12, 2020
9ec704d
Update AdvSimd/
echesakov Mar 12, 2020
c8d6cc4
Address Brian's feedback on GitHub for #33461
echesakov Mar 14, 2020
25fd0d8
Partly address Bruce's feedback on GitHub for #33461
echesakov Mar 14, 2020
77d4077
Revert "lookupSimdSize for Category_MemoryStore should return second …
echesakov Mar 17, 2020
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12 changes: 6 additions & 6 deletions src/coreclr/src/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5230,7 +5230,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
//
// Loads to /Stores from one, two, three, or four SIMD&FP registers
// Loads to and Stores from one, two, three, or four SIMD&FP registers
//

genDefineTempLabel(genCreateTempLabel());
Expand Down Expand Up @@ -5413,7 +5413,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
//
// Loads to /Stores from one, two, three, or four SIMD&FP registers
// Loads to and Stores from one, two, three, or four SIMD&FP registers
//

genDefineTempLabel(genCreateTempLabel());
Expand Down Expand Up @@ -5596,7 +5596,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
//
// Loads to /Stores from one, two, three, or four SIMD&FP registers
// Loads to and Stores from one, two, three, or four SIMD&FP registers
//

genDefineTempLabel(genCreateTempLabel());
Expand Down Expand Up @@ -5779,7 +5779,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
//
// Loads to /Stores from one, two, three, or four SIMD&FP registers
// Loads to and Stores from one, two, three, or four SIMD&FP registers
//

genDefineTempLabel(genCreateTempLabel());
Expand Down Expand Up @@ -5836,7 +5836,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
//
// Loads to /Stores from one, two, three, or four SIMD&FP registers
// Loads to and Stores from one, two, three, or four SIMD&FP registers
//

genDefineTempLabel(genCreateTempLabel());
Expand Down Expand Up @@ -5893,7 +5893,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
//
// Loads to /Stores from one, two, three, or four SIMD&FP registers
// Loads to and Stores from one, two, three, or four SIMD&FP registers
//

genDefineTempLabel(genCreateTempLabel());
Expand Down
16 changes: 8 additions & 8 deletions src/coreclr/src/jit/emitarm64.cpp
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Expand Up @@ -229,8 +229,8 @@ void emitter::emitInsSanityCheck(instrDesc* id)

case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
assert(isVectorRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2())); // SP
if (insOptsAnyArrangement(id->idInsOpt()))
Expand Down Expand Up @@ -959,8 +959,8 @@ bool emitter::emitInsMayWriteToGCReg(instrDesc* id)
case IF_LS_2C: // LS_2C .X.......X.iiiii iiiiP.nnnnnttttt Rt Rn imm(-256..+255) pre/post inc
case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
case IF_LS_3A: // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
case IF_LS_3B: // LS_3B X............... .aaaaannnnnttttt Rt Ra Rn
case IF_LS_3C: // LS_3C X.........iiiiii iaaaaannnnnttttt Rt Ra Rn imm(im7,sh)
Expand Down Expand Up @@ -9762,8 +9762,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
dst += emitOutput_Instr(dst, code);
break;

case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
elemsize = id->idOpSize();
index = id->idSmallCns();
code = emitInsCode(ins, fmt);
Expand Down Expand Up @@ -11645,8 +11645,8 @@ void emitter::emitDispIns(
}
break;

case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
registerListSize = insGetLoadStoreRegisterListSize(id->idIns());
elemsize = id->idOpSize();
emitDispVectorElemList(id->idReg1(), registerListSize, elemsize, id->idSmallCns(), true);
Expand Down
4 changes: 2 additions & 2 deletions src/coreclr/src/jit/emitfmtsarm64.h
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Expand Up @@ -138,8 +138,8 @@ IF_DEF(LS_2D, IS_NONE, NONE) // LS_2D .Q.............. ....ssnnnnnttttt V
// Load single structure and replicate base register
IF_DEF(LS_2E, IS_NONE, NONE) // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn Load/Store multiple structures post-indexed by an immediate
// Load single structure and replicate post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_3A, IS_NONE, NONE) // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
IF_DEF(LS_3B, IS_NONE, NONE) // LS_3B X............... .aaaaannnnnddddd Rd Ra Rn
IF_DEF(LS_3C, IS_NONE, NONE) // LS_3C X.........iiiiii iaaaaannnnnddddd Rd Ra Rn imm(im7,sh)
Expand Down
5 changes: 2 additions & 3 deletions src/coreclr/src/jit/hwintrinsic.cpp
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Expand Up @@ -61,12 +61,11 @@ var_types Compiler::getBaseTypeFromArgIfNeeded(NamedIntrinsic intrinsic,
{
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);

if (category == HW_Category_MemoryStore || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) ||
HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) || HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
{
CORINFO_ARG_LIST_HANDLE arg = sig->args;

if ((category == HW_Category_MemoryStore) || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
{
arg = info.compCompHnd->getArgNext(arg);
}
Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp
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Expand Up @@ -301,6 +301,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, op1Reg);
break;

case NI_AdvSimd_Store:
GetEmitter()->emitIns_R_R(ins, emitSize, op2Reg, op1Reg, opt);
break;

default:
unreached();
}
Expand Down
1 change: 1 addition & 0 deletions src/coreclr/src/jit/hwintrinsiclistarm64.h
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Expand Up @@ -97,6 +97,7 @@ HARDWARE_INTRINSIC(AdvSimd, Or, -
HARDWARE_INTRINSIC(AdvSimd, OrNot, -1, -1, 2, {INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, PopCount, -1, -1, 1, {INS_cnt, INS_cnt, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SqrtScalar, -1, 8, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_fsqrt, INS_fsqrt}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Store, -1, -1, 2, {INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1}, HW_Category_MemoryStore, HW_Flag_NoRMWSemantics|HW_Flag_UnfixedSIMDSize|HW_Flag_SpecialCodeGen|HW_Flag_BaseTypeFromSecondArg)
HARDWARE_INTRINSIC(AdvSimd, Subtract, -1, -1, 2, {INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_fsub, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SubtractScalar, -1, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sub, INS_sub, INS_fsub, INS_fsub}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Xor, -1, -1, 2, {INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize|HW_Flag_Commutative)
Expand Down
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