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[Arm64] Polynomial Multiply Long Intrinsics #36853

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Merged
echesakov merged 9 commits into from
May 22, 2020
Merged

[Arm64] Polynomial Multiply Long Intrinsics #36853

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d074594
Add PolynomialMultiplyWideningLower and PolynomialMultiplyWideningUpp…
echesakov May 21, 2020
f5110b7
Add PolynomialMultiplyWideningLower and PolynomialMultiplyWideningUpp…
echesakov May 21, 2020
a285afb
Update System.Runtime.Intrinsics.Experimental.cs
echesakov May 21, 2020
a6dfec9
Add PolynomialMultiplyWideningLower and PolynomialMultiplyWideningUpp…
echesakov May 21, 2020
414d563
Add Aes PolynomialMultiplyWideningLower in hwintrinsiccodegenarm64.cpp
echesakov May 21, 2020
f76ae51
Add AdvSimd PolynomialMultiplyWideningLower and PolynomialMultiplyWid…
echesakov May 21, 2020
795b130
Add Aes PolynomialMultiplyWideningLower and PolynomialMultiplyWidenin…
echesakov May 21, 2020
4c84a8b
Update Helpers.cs Helpers.tt
echesakov May 21, 2020
5813da9
Update AdvSimd/ Aes/
echesakov May 21, 2020
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6 changes: 6 additions & 0 deletions src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -360,6 +360,11 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
}
break;

case NI_Aes_PolynomialMultiplyWideningLower:
ins = INS_pmull;
opt = INS_OPTS_1D;
break;

default:
ins = HWIntrinsicInfo::lookupIns(intrin.id, intrin.baseType);
break;
Expand Down Expand Up @@ -397,6 +402,7 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
case NI_Crc32_ComputeCrc32C:
case NI_Crc32_Arm64_ComputeCrc32:
case NI_Crc32_Arm64_ComputeCrc32C:
case NI_Aes_PolynomialMultiplyWideningLower:
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
break;

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4 changes: 4 additions & 0 deletions src/coreclr/src/jit/hwintrinsiclistarm64.h
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Expand Up @@ -147,6 +147,8 @@ HARDWARE_INTRINSIC(AdvSimd, Not, -
HARDWARE_INTRINSIC(AdvSimd, Or, -1, 2, {INS_orr, INS_orr, INS_orr, INS_orr, INS_orr, INS_orr, INS_orr, INS_orr, INS_orr, INS_orr}, HW_Category_SimpleSIMD, HW_Flag_Commutative)
HARDWARE_INTRINSIC(AdvSimd, OrNot, -1, 2, {INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn}, HW_Category_SimpleSIMD, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(AdvSimd, PolynomialMultiply, -1, 2, {INS_pmul, INS_pmul, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_Commutative)
HARDWARE_INTRINSIC(AdvSimd, PolynomialMultiplyWideningLower, 8, 2, {INS_pmull, INS_pmull, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_Commutative|HW_Flag_BaseTypeFromFirstArg)
HARDWARE_INTRINSIC(AdvSimd, PolynomialMultiplyWideningUpper, 16, 2, {INS_pmull2, INS_pmull2, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_Commutative|HW_Flag_BaseTypeFromFirstArg)
HARDWARE_INTRINSIC(AdvSimd, PopCount, -1, 1, {INS_cnt, INS_cnt, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(AdvSimd, ReciprocalEstimate, -1, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_urecpe, INS_invalid, INS_invalid, INS_frecpe, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(AdvSimd, ReciprocalSquareRootEstimate, -1, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ursqrte, INS_invalid, INS_invalid, INS_frsqrte, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoFlag)
Expand Down Expand Up @@ -262,6 +264,8 @@ HARDWARE_INTRINSIC(Aes, Decrypt, 1
HARDWARE_INTRINSIC(Aes, Encrypt, 16, 2, {INS_invalid, INS_aese, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Aes, InverseMixColumns, 16, 1, {INS_invalid, INS_aesimc, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(Aes, MixColumns, 16, 1, {INS_invalid, INS_aesmc, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(Aes, PolynomialMultiplyWideningLower, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_pmull, INS_pmull, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_SpecialCodeGen|HW_Flag_Commutative|HW_Flag_BaseTypeFromFirstArg)
HARDWARE_INTRINSIC(Aes, PolynomialMultiplyWideningUpper, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_pmull2, INS_pmull2, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_Commutative|HW_Flag_BaseTypeFromFirstArg)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size NumArg Instructions Category Flags
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4 changes: 4 additions & 0 deletions src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_r.csproj
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Original file line number Diff line number Diff line change
Expand Up @@ -742,6 +742,10 @@
<Compile Include="PolynomialMultiply.Vector64.SByte.cs" />
<Compile Include="PolynomialMultiply.Vector128.Byte.cs" />
<Compile Include="PolynomialMultiply.Vector128.SByte.cs" />
<Compile Include="PolynomialMultiplyWideningLower.Vector64.Byte.cs" />
<Compile Include="PolynomialMultiplyWideningLower.Vector64.SByte.cs" />
<Compile Include="PolynomialMultiplyWideningUpper.Vector128.Byte.cs" />
<Compile Include="PolynomialMultiplyWideningUpper.Vector128.SByte.cs" />
<Compile Include="PopCount.Vector64.Byte.cs" />
<Compile Include="PopCount.Vector64.SByte.cs" />
<Compile Include="PopCount.Vector128.Byte.cs" />
Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_ro.csproj
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Original file line number Diff line number Diff line change
Expand Up @@ -742,6 +742,10 @@
<Compile Include="PolynomialMultiply.Vector64.SByte.cs" />
<Compile Include="PolynomialMultiply.Vector128.Byte.cs" />
<Compile Include="PolynomialMultiply.Vector128.SByte.cs" />
<Compile Include="PolynomialMultiplyWideningLower.Vector64.Byte.cs" />
<Compile Include="PolynomialMultiplyWideningLower.Vector64.SByte.cs" />
<Compile Include="PolynomialMultiplyWideningUpper.Vector128.Byte.cs" />
<Compile Include="PolynomialMultiplyWideningUpper.Vector128.SByte.cs" />
<Compile Include="PopCount.Vector64.Byte.cs" />
<Compile Include="PopCount.Vector64.SByte.cs" />
<Compile Include="PopCount.Vector128.Byte.cs" />
Expand Down
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