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[RyuJIT] Add "rorx" instruction (BMI2) and emit it instead of "rol" when possible #41772

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Merged
CarolEidt merged 15 commits into from
Sep 29, 2020
Merged

[RyuJIT] Add "rorx" instruction (BMI2) and emit it instead of "rol" when possible #41772

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562a10c
Use rorx instead of rol when possible
EgorBo Sep 2, 2020
928c55d
check for BMI2 availability
EgorBo Sep 3, 2020
ab495fc
Update codegenxarch.cpp
EgorBo Sep 3, 2020
ddb3382
Update codegenxarch.cpp
EgorBo Sep 3, 2020
462719c
Merge branch 'master' of github.com:dotnet/runtime into add-rorx-inst…
EgorBo Sep 3, 2020
b85c87b
formatting
EgorBo Sep 3, 2020
d808b86
Merge branch 'master' of github.com:dotnet/runtime into add-rorx-inst…
EgorBo Sep 4, 2020
739007b
handle GT_ROR
EgorBo Sep 4, 2020
c5933e9
clean up
EgorBo Sep 4, 2020
609af9e
Don't emit rorx when targetReg == operandReg
EgorBo Sep 5, 2020
1b3e055
Merge branch 'master' of github.com:dotnet/runtime into add-rorx-inst…
EgorBo Sep 9, 2020
5a36432
emit rorx only for long integers
EgorBo Sep 9, 2020
da9d166
wrap with TARGET_64BIT
EgorBo Sep 9, 2020
7cbb1ce
clean up
EgorBo Sep 9, 2020
9e9b1cb
clean up
EgorBo Sep 9, 2020
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emit rorx only for long integers
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@EgorBo
EgorBo committed Sep 9, 2020
commit 5a36432fdc46ea9470c5a2ccd109dec59243accb
11 changes: 5 additions & 6 deletions src/coreclr/src/jit/codegenxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4083,16 +4083,15 @@ void CodeGen::genCodeForShift(GenTree* tree)
}
else
{
int typeWidth = genTypeSize(genActualType(targetType)) * 8;
int shiftByValue = (int)shiftBy->AsIntConCommon()->IconValue();

// Try to emit rorx if BMI2 is available instead of mov+rol
if (compiler->compOpportunisticallyDependsOn(InstructionSet_BMI2) && (tree->GetRegNum() != operandReg) &&
tree->OperIs(GT_ROL, GT_ROR) && (shiftByValue > 0) && (shiftByValue < typeWidth))
// it makes sense only for 64bit integers
if ((genActualType(targetType) == TYP_LONG) && (tree->GetRegNum() != operandReg) &&
compiler->compOpportunisticallyDependsOn(InstructionSet_BMI2) && tree->OperIs(GT_ROL, GT_ROR) &&
(shiftByValue > 0) && (shiftByValue < 64))
{
assert((typeWidth == 32) || (typeWidth == 64));

int value = tree->OperIs(GT_ROL) ? (typeWidth - shiftByValue) : shiftByValue;
const int value = tree->OperIs(GT_ROL) ? (64 - shiftByValue) : shiftByValue;
GetEmitter()->emitIns_R_R_I(INS_rorx, size, tree->GetRegNum(), operandReg, value);
}
else
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