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Faster unsigned division by constants #52893

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Merged
tannergooding merged 13 commits into from
May 18, 2021
Merged

Faster unsigned division by constants #52893

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ee6385f
Faster unsigned division by constants
pentp Mar 13, 2021
cfc7e34
Fix Arm build and add some tests.
pentp Mar 14, 2021
299b6e1
Improve register allocation
pentp Mar 14, 2021
eacfd46
Fix ARM64 codegen
pentp Mar 14, 2021
8b0fc7d
Fix MULHI flags
pentp Mar 15, 2021
c50f0fe
Remove ARM32 codegen
pentp Mar 15, 2021
f595fe6
Widen 32bit UDIV to 64bit MULHI when possible. Improve register alloc…
pentp Mar 16, 2021
58c5564
Always widen 32bit UDIV to 64bit MUL/MULHI
pentp Mar 16, 2021
b6f4b54
Cleanup
pentp Mar 16, 2021
41c2c06
Final optimization
pentp Mar 17, 2021
ad3f5ff
Fix typo
pentp Mar 17, 2021
176562d
Rebase and use inst_Mov instead of inst_RV_RV(INS_mov)
pentp May 18, 2021
935f098
Fix formatting (1 space)
pentp May 18, 2021
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Fix ARM64 codegen
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@pentp
pentp committed May 18, 2021
commit eacfd46a29b758a65cebe308c4da6d520995e131
2 changes: 1 addition & 1 deletion src/coreclr/jit/codegenarmarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4233,7 +4233,7 @@ void CodeGen::genCodeForIncSaturate(GenTree* tree)

#ifdef TARGET_ARM64
GetEmitter()->emitIns_R_R_I(INS_adds, emitActualTypeSize(tree), targetReg, operandReg, 1);
GetEmitter()->emitIns_R_R_R_COND(INS_csinv, emitActualTypeSize(tree), targetReg, targetReg, REG_ZR, INS_COND_LO);
GetEmitter()->emitIns_R_R_COND(INS_cinv, emitActualTypeSize(tree), targetReg, targetReg, INS_COND_HS);
#else
regNumber tmpReg = tree->GetSingleTempReg();
GetEmitter()->emitIns_R_I(INS_mov, emitActualTypeSize(tree), tmpReg, 0);
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