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Update instruction table to capture the correct state of EFlags #53806

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Merged
5 commits merged into from
Jun 8, 2021
Merged

Update instruction table to capture the correct state of EFlags #53806

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3fbe767
Update instruction table with accurate EFlags information
kunalspathak Jun 7, 2021
99e535e
Revert "Add issues.targets entry for the GitHub_13822 test to make CI…
kunalspathak Jun 7, 2021
d373963
minor fixup
kunalspathak Jun 7, 2021
a607bf2
Fix some more instructions
kunalspathak Jun 7, 2021
41bc701
review comments
kunalspathak Jun 8, 2021
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Fix some more instructions
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@kunalspathak
kunalspathak committed Jun 7, 2021
commit a607bf2306291ba6b750e60b09bdeeae77f463af
16 changes: 8 additions & 8 deletions src/coreclr/jit/instrsxarch.h
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Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ INST4(lea, "lea", IUM_WR, BAD_CODE, BAD_CODE,

// Note that emitter has only partial support for BT. It can only emit the reg,reg form
// and the registers need to be reversed to get the correct encoding.
INST3(bt, "bt", IUM_RD, 0x0F00A3, BAD_CODE, 0x0F00A3, Undefined_OF | Undefined_SF | Undefined_AF | Undefined_PF | Writes_CF )
INST3(bt, "bt", IUM_RD, 0x0F00A3, BAD_CODE, 0x0F00A3, Undefined_OF | Undefined_SF | Undefined_ZF | Undefined_AF | Undefined_PF | Writes_CF )

INST3(bsf, "bsf", IUM_WR, BAD_CODE, BAD_CODE, 0x0F00BC, Undefined_OF | Undefined_SF | Writes_ZF | Undefined_AF | Undefined_PF | Undefined_CF )
INST3(bsr, "bsr", IUM_WR, BAD_CODE, BAD_CODE, 0x0F00BD, Undefined_OF | Undefined_SF | Writes_ZF | Undefined_AF | Undefined_PF | Undefined_CF )
Expand Down Expand Up @@ -303,10 +303,10 @@ INST3(cvttpd2dq, "cvttpd2dq", IUM_WR, BAD_CODE, BAD_CODE,
INST3(cvtdq2pd, "cvtdq2pd", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0xE6), INS_FLAGS_None) // cvt packed DWORDs to doubles

// SSE2 comparison instructions
INST3(comiss, "comiss", IUM_RD, BAD_CODE, BAD_CODE, PCKFLT(0x2F), Resets_CF | Resets_SF | Writes_ZF | Resets_AF | Writes_PF | Writes_CF ) // ordered compare singles
INST3(comisd, "comisd", IUM_RD, BAD_CODE, BAD_CODE, PCKDBL(0x2F), Resets_CF | Resets_SF | Writes_ZF | Resets_AF | Writes_PF | Writes_CF ) // ordered compare doubles
INST3(ucomiss, "ucomiss", IUM_RD, BAD_CODE, BAD_CODE, PCKFLT(0x2E), Resets_CF | Resets_SF | Writes_ZF | Resets_AF | Writes_PF | Writes_CF ) // unordered compare singles
INST3(ucomisd, "ucomisd", IUM_RD, BAD_CODE, BAD_CODE, PCKDBL(0x2E), Resets_CF | Resets_SF | Writes_ZF | Resets_AF | Writes_PF | Writes_CF ) // unordered compare doubles
INST3(comiss, "comiss", IUM_RD, BAD_CODE, BAD_CODE, PCKFLT(0x2F), Resets_OF | Resets_SF | Writes_ZF | Resets_AF | Writes_PF | Writes_CF ) // ordered compare singles
INST3(comisd, "comisd", IUM_RD, BAD_CODE, BAD_CODE, PCKDBL(0x2F), Resets_OF | Resets_SF | Writes_ZF | Resets_AF | Writes_PF | Writes_CF ) // ordered compare doubles
INST3(ucomiss, "ucomiss", IUM_RD, BAD_CODE, BAD_CODE, PCKFLT(0x2E), Resets_OF | Resets_SF | Writes_ZF | Resets_AF | Writes_PF | Writes_CF ) // unordered compare singles
INST3(ucomisd, "ucomisd", IUM_RD, BAD_CODE, BAD_CODE, PCKDBL(0x2E), Resets_OF | Resets_SF | Writes_ZF | Resets_AF | Writes_PF | Writes_CF ) // unordered compare doubles

// SSE2 packed single/double comparison operations.
// Note that these instructions not only compare but also overwrite the first source.
Expand Down Expand Up @@ -659,10 +659,10 @@ INST2(sar_N, "sar", IUM_RW, 0x0038C0, 0x0038C0,


// id nm um mr flags
INST1(r_movsb, "rep movsb", IUM_RD, 0x00A4F3, INS_FLAGS_None )
INST1(r_movsd, "rep movsd", IUM_RD, 0x00A5F3, INS_FLAGS_None )
INST1(r_movsb, "rep movsb", IUM_RD, 0x00A4F3, Reads_DF )
INST1(r_movsd, "rep movsd", IUM_RD, 0x00A5F3, Reads_DF )
#if defined(TARGET_AMD64)
INST1(r_movsq, "rep movsq", IUM_RD, 0xF3A548, INS_FLAGS_None )
INST1(r_movsq, "rep movsq", IUM_RD, 0xF3A548, Reads_DF )
#endif // defined(TARGET_AMD64)
INST1(movsb, "movsb", IUM_RD, 0x0000A4, Reads_DF )
INST1(movsd, "movsd", IUM_RD, 0x0000A5, Reads_DF )
Expand Down