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[release/7.0] Ensure that the SSE fallback for Vector3.Dot masks off the unused element of op1 and op2 #74980

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Merged
carlossanlop merged 3 commits into from
Sep 2, 2022
Merged

[release/7.0] Ensure that the SSE fallback for Vector3.Dot masks off the unused element of op1 and op2 #74980

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3e04901
Ensure that the SSE fallback for Vector3.Dot masks off the unused ele…
tannergooding Sep 1, 2022
0a84cba
Applying formatting patch
tannergooding Sep 1, 2022
e3b05f1
Ensure we use TYP_SIMD16 in for the simdType when generating the fall…
tannergooding Sep 1, 2022
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Applying formatting patch
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@tannergooding
tannergooding authored and github-actions committed Sep 2, 2022
commit 0a84cbacb64a01462027bdf2e18a2d92d0c19506
6 changes: 3 additions & 3 deletions src/coreclr/jit/lowerxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3423,7 +3423,7 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node)
// from including it in the computed result. We need to do this for both op1 and
// op2 in case one of them is `NaN` (because Zero * NaN == NaN)

simd12_t simd12Val = { };
simd12_t simd12Val = {};

simd12Val.i32[0] = -1;
simd12Val.i32[1] = -1;
Expand All @@ -3448,7 +3448,7 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node)
// ...

GenTreeVecCon* vecCon1 = comp->gtNewVconNode(simdType, simdBaseJitType);
vecCon1->gtSimd12Val = simd12Val;
vecCon1->gtSimd12Val = simd12Val;

BlockRange().InsertAfter(op1, vecCon1);

Expand Down Expand Up @@ -3477,7 +3477,7 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node)
// ...

GenTreeVecCon* vecCon2 = comp->gtNewVconNode(simdType, simdBaseJitType);
vecCon2->gtSimd12Val = simd12Val;
vecCon2->gtSimd12Val = simd12Val;

BlockRange().InsertAfter(op2, vecCon2);

Expand Down