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982daf3
Experimental
davidwrighton Oct 21, 2022
f443bfa
Experiment
davidwrighton Oct 21, 2022
2fa62aa
More progress
davidwrighton Oct 28, 2022
55a5bb6
Increase accuracy of comments around range section locking
davidwrighton Nov 14, 2022
f5357bb
Changes to RangeListMap to make it work
davidwrighton Nov 29, 2022
1abc9c6
Add low bit check indirection
davidwrighton Nov 29, 2022
5eee830
Rework to passing down the current locking status
davidwrighton Nov 29, 2022
e4fb4db
Allocation of RangeSection and freeing added, as well as testing for …
davidwrighton Nov 29, 2022
6505eb5
Fix some naming
davidwrighton Nov 29, 2022
62b0376
Miraculously it builds!
davidwrighton Nov 30, 2022
ebadf2a
May actually work. DAC access known to be broken.
davidwrighton Nov 30, 2022
c6fb27c
Merge branch 'main' of https://github.com/dotnet/runtime into rangeli…
davidwrighton Nov 30, 2022
3ecfff8
Fix handling of unwind table
davidwrighton Dec 1, 2022
209877b
Seems to work well on WinX64
davidwrighton Dec 2, 2022
50712b7
Fix performance of the DelegateConstruct method
davidwrighton Dec 2, 2022
38acd5c
It should build everywhere now
davidwrighton Dec 2, 2022
9148e31
Delete temporary bits
davidwrighton Dec 2, 2022
dce4bb1
Fix Windows builds
davidwrighton Dec 6, 2022
518011c
Fix contract issues
davidwrighton Dec 6, 2022
6db0e70
Fix CodeRangeMapRangeList to handle interval correctly
davidwrighton Dec 6, 2022
c8a74e2
It builds on Linux!
davidwrighton Dec 6, 2022
2a012b2
Make it even more lock free
davidwrighton Dec 6, 2022
de97c17
Remove confusion around Range interval specification Some uses were r…
davidwrighton Dec 8, 2022
a493cde
Attempt to appease the GCC build
davidwrighton Dec 8, 2022
1507207
Fix the math around fragment handling and index calculations
davidwrighton Dec 9, 2022
493225b
Make the RangeSectionMap available to the DAC
davidwrighton Dec 12, 2022
a24184d
Move to 5 levels for 64bit RangeSectionMap. 8KB chunks are a waste of…
davidwrighton Dec 12, 2022
af74f62
Remove unnecessary memory dereferences
davidwrighton Dec 12, 2022
4b4b15d
Tweak algorithm to allow for R2R checks to be entirely lock-free
davidwrighton Dec 13, 2022
c01de3f
Update comment
davidwrighton Dec 13, 2022
8563905
Enable support for freeing portion of the CodeRangeMap which are no l…
davidwrighton Dec 13, 2022
eefa191
Fix GCC noticed signed/unsigned mismatch
davidwrighton Dec 13, 2022
67cefc5
Fix next GCC noticed signed/unsigned mismatch
davidwrighton Dec 16, 2022
05a35a9
Merge branch 'main' of https://github.com/dotnet/runtime into rangeli…
davidwrighton Feb 21, 2023
48ead1f
Adjust to feedback
davidwrighton Feb 22, 2023
ea79cb2
Merge branch 'main' of https://github.com/dotnet/runtime into rangeli…
davidwrighton Mar 4, 2023
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Move to 5 levels for 64bit RangeSectionMap. 8KB chunks are a waste of…
… memory
  • Loading branch information
davidwrighton committed Dec 12, 2022
commit a24184dc1305215721b9eca4ec1a74bd6215e8ff
28 changes: 18 additions & 10 deletions src/coreclr/vm/codeman.h
Original file line number Diff line number Diff line change
Expand Up @@ -735,10 +735,11 @@ enum class RangeSectionLockState
// For 64bit, we work with 8KB chunks of memory holding pointers to the next level. This provides 10 bits of address resolution per level.
// For *reasons* the X64 hardware is limited to 57bits of addressable address space, and the minimum granularity that makes sense for range lists is 64KB (or every 2^16 bits)
// Similarly the Arm64 specification requires addresses to use at most 52 bits. Thus we use the maximum addressable range of X64 to provide the real max range
// So the first level is bits [56:47] -> L4
// Then [46:37] -> L3
// [36:27] -> L2
// [26:17] -> L1
// So the first level is bits [56:49] -> L5
// Then [48:41] -> L4
// [40:33] -> L3
// [32:25] -> L2
// [24:17] -> L1
// This leaves 17 bits of the address to be handled by the RangeSection linked list
//
// For 32bit VA processes, use 1KB chunks holding pointers to the next level. This provides 8 bites of address resolution per level. [31:24] and [23:16].
Expand Down Expand Up @@ -839,7 +840,7 @@ class RangeSectionMap
};

#ifdef TARGET_64BIT
static const uintptr_t entriesPerMapLevel = 1024;
static const uintptr_t entriesPerMapLevel = 256;
#else
static const uintptr_t entriesPerMapLevel = 256;
#endif
Expand All @@ -849,12 +850,13 @@ class RangeSectionMap
typedef DPTR(RangeSectionL1) RangeSectionL2[entriesPerMapLevel];
typedef DPTR(RangeSectionL2) RangeSectionL3[entriesPerMapLevel];
typedef DPTR(RangeSectionL3) RangeSectionL4[entriesPerMapLevel];
typedef DPTR(RangeSectionL4) RangeSectionL5[entriesPerMapLevel];

#ifdef TARGET_64BIT
typedef RangeSectionL4 RangeSectionTopLevel;
static const uintptr_t mapLevels = 4;
typedef RangeSectionL5 RangeSectionTopLevel;
static const uintptr_t mapLevels = 5;
static const uintptr_t maxSetBit = 56; // This is 0 indexed
static const uintptr_t bitsPerLevel = 10;
static const uintptr_t bitsPerLevel = 8;
#else
typedef RangeSectionL2 RangeSectionTopLevel;
static const uintptr_t mapLevels = 2;
Expand Down Expand Up @@ -922,7 +924,10 @@ class RangeSectionMap
{
uintptr_t level = mapLevels + 1;
#ifdef TARGET_64BIT
auto _RangeSectionL3 = EnsureLevel(address, &_topLevel, --level);
auto _RangeSectionL4 = EnsureLevel(address, &_topLevel, --level);
if (_RangeSectionL4 == NULL)
return NULL; // Failure case
auto _RangeSectionL3 = EnsureLevel(address, _RangeSectionL4, --level);
if (_RangeSectionL3 == NULL)
return NULL; // Failure case
auto _RangeSectionL2 = EnsureLevel(address, _RangeSectionL3, --level);
Expand All @@ -946,7 +951,10 @@ class RangeSectionMap
PTR_RangeSectionFragment GetRangeSectionForAddress(TADDR address, RangeSectionLockState *pLockState)
{
#ifdef TARGET_64BIT
auto _RangeSectionL4 = VolatileLoad(&_topLevel);
auto _RangeSectionL5 = VolatileLoad(&_topLevel);
if (_RangeSectionL5 == NULL)
return NULL;
auto _RangeSectionL4 = (*_RangeSectionL5)[EffectiveBitsForLevel(address, 4)];
if (_RangeSectionL4 == NULL)
return NULL;
auto _RangeSectionL3 = (*_RangeSectionL4)[EffectiveBitsForLevel(address, 4)];
Expand Down