Avx512 upper regs variable (Draft)

src/coreclr/jit/compiler.cpp

@@ -3325,6 +3325,30 @@ void Compiler::compInitOptions(JitFlags* jitFlags)
         opts.compJitSaveFpLrWithCalleeSavedRegisters = JitConfig.JitSaveFpLrWithCalleeSavedRegisters();
     }
 #endif // defined(DEBUG) && defined(TARGET_ARM64)
+
+#if defined(TARGET_AMD64)
+    rbmAllFloat            = RBM_ALLFLOAT_INIT;
+    rbmFltCalleeTrash      = RBM_FLT_CALLEE_TRASH_INIT;
+    rbmCntCalleeTrashFloat = CNT_CALLEE_TRASH_FLOAT_INIT;
+
+    if (DoJitStressEvexEncoding())
+    {
+        rbmAllFloat |= RBM_HIGHFLOAT;
+        rbmFltCalleeTrash |= RBM_HIGHFLOAT;
+        rbmCntCalleeTrashFloat += 16;
+    }
+    rbmCalleeTrash                    = RBM_CALLEE_TRASH_INIT;
+    rbmCalleeTrashNoGC                = RBM_CALLEE_TRASH_NOGC_INIT;
+    rbmCalleeTrashWriteBarrier        = RBM_CALLEE_TRASH_WRITEBARRIER_INIT;
+    rbmCalleeGCTrashWriteBarrier      = RBM_CALLEE_GCTRASH_WRITEBARRIER_INIT;
+    rbmCalleeTrashWriteBarrierByref   = RBM_CALLEE_TRASH_WRITEBARRIER_BYREF_INIT;
+    rbmCalleeGCTrashWriteBarrierByref = RBM_CALLEE_GCTRASH_WRITEBARRIER_BYREF_INIT;
+    rbmStopForGCTrash                 = RBM_STOP_FOR_GC_TRASH_INIT;
+    rbmInitPInvokeFrameTrash          = RBM_INIT_PINVOKE_FRAME_TRASH_INIT;
+    rbmProfilerEnterTrash             = RBM_PROFILER_ENTER_TRASH_INIT;
+    rbmProfilerLeaveTrash             = RBM_PROFILER_LEAVE_TRASH_INIT;
+    rbmProfilerTailcallTrash          = RBM_PROFILER_TAILCALL_TRASH_INIT;
+#endif // TARGET_AMD64
 }
 
 #ifdef DEBUG
@@ -10258,3 +10282,25 @@ void Compiler::EnregisterStats::Dump(FILE* fout) const
     PRINT_STATS(m_dispatchRetBuf, m_addrExposed);
 }
 #endif // TRACK_ENREG_STATS
+
+#if defined(TARGET_AMD64)
+// The following are for initializing register allocator "constants" defined in targetamd.h
+// that now depend upon runtime ISA information, e.g., the presence of AVX512F/VL, which increases
+// the number of simd (xmm,ymm, and zmm) registers from 16 to 32.
+// As only 64-bit xarch has the capability to have the additional registers, we limit the changes
+// to TARGET_AMD64 only.
+regMaskTP rbmAllFloat;
+regMaskTP rbmFltCalleeTrash;
+regMaskTP rbmCalleeTrash;
+regMaskTP rbmCalleeTrashNoGC;
+regMaskTP rbmCalleeTrashWriteBarrier;
+regMaskTP rbmCalleeGCTrashWriteBarrier;
+regMaskTP rbmCalleeTrashWriteBarrierByref;
+regMaskTP rbmCalleeGCTrashWriteBarrierByref;
+regMaskTP rbmStopForGCTrash;
+regMaskTP rbmProfilerTailcallTrash;
+regMaskTP rbmInitPInvokeFrameTrash;
+regMaskTP rbmProfilerEnterTrash;
+regMaskTP rbmProfilerLeaveTrash;
+unsigned  rbmCntCalleeTrashFloat;
+#endif // TARGET_AMD64

src/coreclr/jit/compiler.h

@@ -11603,6 +11603,32 @@ extern const BYTE genActualTypes[];
 
 /*****************************************************************************/
 
+/*****************************************************************************/
+
+#if defined(TARGET_AMD64)
+// The following are for initializing register allocator "constants" defined in targetamd.h
+// that now depend upon runtime ISA information, e.g., the presence of AVX512F/VL, which increases
+// the number of simd (xmm,ymm, and zmm) registers from 16 to 32.
+// As only 64-bit xarch has the capability to have the additional registers, we limit the changes
+// to TARGET_AMD64 only.
+extern regMaskTP rbmAllFloat;
+extern regMaskTP rbmFltCalleeTrash;
+extern regMaskTP rbmCalleeTrash;
+extern regMaskTP rbmCalleeTrashNoGC;
+extern regMaskTP rbmCalleeTrashWriteBarrier;
+extern regMaskTP rbmCalleeGCTrashWriteBarrier;
+extern regMaskTP rbmCalleeTrashWriteBarrierByref;
+extern regMaskTP rbmCalleeGCTrashWriteBarrierByref;
+extern regMaskTP rbmStopForGCTrash;
+extern regMaskTP rbmProfilerTailcallTrash;
+extern regMaskTP rbmInitPInvokeFrameTrash;
+extern regMaskTP rbmProfilerEnterTrash;
+extern regMaskTP rbmProfilerLeaveTrash;
+extern unsigned  rbmCntCalleeTrashFloat;
+#endif // TARGET_AMD64
+
+/*****************************************************************************/
+
 #ifdef DEBUG
 void dumpConvertedVarSet(Compiler* comp, VARSET_VALARG_TP vars);
 #endif // DEBUG

src/coreclr/jit/emit.h

@@ -1121,6 +1121,28 @@ class emitter
             idAddr()->_idReg4 = reg;
             assert(reg == idAddr()->_idReg4);
         }
+        bool idHasReg3() const
+        {
+            switch (idInsFmt())
+            {
+                case IF_RWR_RRD_RRD:
+                case IF_RWR_RRD_RRD_CNS:
+                case IF_RWR_RRD_RRD_RRD:
+                    return true;
+                default:
+                    return false;
+            }
+        }
+        bool idHasReg4() const
+        {
+            switch (idInsFmt())
+            {
+                case IF_RWR_RRD_RRD_RRD:
+                    return true;
+                default:
+                    return false;
+            }
+        }
 #endif // defined(TARGET_XARCH)
 #ifdef TARGET_ARMARCH
         insOpts idInsOpt() const

src/coreclr/jit/emitinl.h

@@ -214,7 +214,8 @@ inline ssize_t emitter::emitGetInsAmdAny(instrDesc* id)
 
 /*static*/ inline void emitter::emitEncodeCallGCregs(regMaskTP regmask, instrDesc* id)
 {
-    assert((regmask & RBM_CALLEE_TRASH) == 0);
+    // TODO-XARCH-AVX512 global defined in compiler.h, not in scope here
+    // assert((regmask & RBM_CALLEE_TRASH) == 0);
 
     unsigned encodeMask;