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anthonycanino wants to merge 7 commits into from
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Avx512 upper regs macro #79423

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40807a3
Change regMask_enum and regMaskTP to unsigned __int64_t on AMD64.
anthonycanino Oct 27, 2022
90f7d44
(WIP) Add upper 16 SIMD registers to allocator.
anthonycanino Oct 28, 2022
86b56dd
Refactor code to use `const instrDesc *` instead of `instruction`.
anthonycanino Oct 31, 2022
9768d11
Add EVEX high SIMD reg bits to emitter paths.
anthonycanino Nov 3, 2022
b2d4da6
Limit high SIMD reg to compatible intrinsics lsra build.
anthonycanino Nov 14, 2022
e3cd148
Allow `compiler` to be passed into the CALLEE TRASH macros.
anthonycanino Nov 30, 2022
7bc1399
Fixing some more of the macros.
anthonycanino Dec 8, 2022
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Fixing some more of the macros.
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@anthonycanino
anthonycanino committed Dec 8, 2022
commit 7bc13997c0b9fa20e81f697661e4651880dee14f
10 changes: 5 additions & 5 deletions src/coreclr/jit/codegenarm.cpp
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Expand Up @@ -1909,7 +1909,7 @@ void CodeGen::genAllocLclFrame(unsigned frameSize, regNumber initReg, bool* pIni
void CodeGen::genPushFltRegs(regMaskTP regMask)
{
assert(regMask != 0); // Don't call uness we have some registers to push
assert((regMask & RBM_ALLFLOAT) == regMask); // Only floasting point registers should be in regMask
assert((regMask & RBM_ALLFLOAT(compiler)) == regMask); // Only floasting point registers should be in regMask

regNumber lowReg = genRegNumFromMask(genFindLowestBit(regMask));
int slots = genCountBits(regMask);
Expand All @@ -1928,7 +1928,7 @@ void CodeGen::genPushFltRegs(regMaskTP regMask)
void CodeGen::genPopFltRegs(regMaskTP regMask)
{
assert(regMask != 0); // Don't call uness we have some registers to pop
assert((regMask & RBM_ALLFLOAT) == regMask); // Only floasting point registers should be in regMask
assert((regMask & RBM_ALLFLOAT(compiler)) == regMask); // Only floasting point registers should be in regMask

regNumber lowReg = genRegNumFromMask(genFindLowestBit(regMask));
int slots = genCountBits(regMask);
Expand Down Expand Up @@ -2135,7 +2135,7 @@ void CodeGen::genPopCalleeSavedRegisters(bool jmpEpilog)
assert(compiler->compGeneratingEpilog);

regMaskTP maskPopRegs = regSet.rsGetModifiedRegsMask() & RBM_CALLEE_SAVED;
regMaskTP maskPopRegsFloat = maskPopRegs & RBM_ALLFLOAT;
regMaskTP maskPopRegsFloat = maskPopRegs & RBM_ALLFLOAT(compiler);
regMaskTP maskPopRegsInt = maskPopRegs & ~maskPopRegsFloat;

// First, pop float registers
Expand Down Expand Up @@ -2295,7 +2295,7 @@ void CodeGen::genFuncletProlog(BasicBlock* block)

compiler->unwindBegProlog();

regMaskTP maskPushRegsFloat = genFuncletInfo.fiSaveRegs & RBM_ALLFLOAT;
regMaskTP maskPushRegsFloat = genFuncletInfo.fiSaveRegs & RBM_ALLFLOAT(compiler);
regMaskTP maskPushRegsInt = genFuncletInfo.fiSaveRegs & ~maskPushRegsFloat;

regMaskTP maskStackAlloc = genStackAllocRegisterMask(genFuncletInfo.fiSpDelta, maskPushRegsFloat);
Expand Down Expand Up @@ -2391,7 +2391,7 @@ void CodeGen::genFuncletEpilog()
/* The saved regs info saves the LR register. We need to pop the PC register to return */
assert(genFuncletInfo.fiSaveRegs & RBM_LR);

regMaskTP maskPopRegsFloat = genFuncletInfo.fiSaveRegs & RBM_ALLFLOAT;
regMaskTP maskPopRegsFloat = genFuncletInfo.fiSaveRegs & RBM_ALLFLOAT(compiler);
regMaskTP maskPopRegsInt = genFuncletInfo.fiSaveRegs & ~maskPopRegsFloat;

regMaskTP maskStackAlloc = genStackAllocRegisterMask(genFuncletInfo.fiSpDelta, maskPopRegsFloat);
Expand Down
10 changes: 5 additions & 5 deletions src/coreclr/jit/codegenarm64.cpp
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Expand Up @@ -910,7 +910,7 @@ void CodeGen::genSaveCalleeSavedRegistersHelp(regMaskTP regsToSaveMask, int lowe

// Save integer registers at higher addresses than floating-point registers.

regMaskTP maskSaveRegsFloat = regsToSaveMask & RBM_ALLFLOAT;
regMaskTP maskSaveRegsFloat = regsToSaveMask & RBM_ALLFLOAT(compiler);
regMaskTP maskSaveRegsInt = regsToSaveMask & ~maskSaveRegsFloat;

if (maskSaveRegsFloat != RBM_NONE)
Expand Down Expand Up @@ -1027,7 +1027,7 @@ void CodeGen::genRestoreCalleeSavedRegistersHelp(regMaskTP regsToRestoreMask, in

// Save integer registers at higher addresses than floating-point registers.

regMaskTP maskRestoreRegsFloat = regsToRestoreMask & RBM_ALLFLOAT;
regMaskTP maskRestoreRegsFloat = regsToRestoreMask & RBM_ALLFLOAT(compiler);
regMaskTP maskRestoreRegsInt = regsToRestoreMask & ~maskRestoreRegsFloat;

// Restore in the opposite order of saving.
Expand Down Expand Up @@ -1352,7 +1352,7 @@ void CodeGen::genFuncletProlog(BasicBlock* block)

compiler->unwindBegProlog();

regMaskTP maskSaveRegsFloat = genFuncletInfo.fiSaveRegs & RBM_ALLFLOAT;
regMaskTP maskSaveRegsFloat = genFuncletInfo.fiSaveRegs & RBM_ALLFLOAT(compiler);
regMaskTP maskSaveRegsInt = genFuncletInfo.fiSaveRegs & ~maskSaveRegsFloat;

// Funclets must always save LR and FP, since when we have funclets we must have an FP frame.
Expand Down Expand Up @@ -1556,7 +1556,7 @@ void CodeGen::genFuncletEpilog()
unwindStarted = true;
}

regMaskTP maskRestoreRegsFloat = genFuncletInfo.fiSaveRegs & RBM_ALLFLOAT;
regMaskTP maskRestoreRegsFloat = genFuncletInfo.fiSaveRegs & RBM_ALLFLOAT(compiler);
regMaskTP maskRestoreRegsInt = genFuncletInfo.fiSaveRegs & ~maskRestoreRegsFloat;

// Funclets must always save LR and FP, since when we have funclets we must have an FP frame.
Expand Down Expand Up @@ -5256,7 +5256,7 @@ void CodeGen::genSIMDIntrinsicInitN(GenTreeSIMD* simdNode)
{
// Note that we cannot use targetReg before consuming all float source operands.
// Therefore use an internal temp register
vectorReg = simdNode->GetSingleTempReg(RBM_ALLFLOAT);
vectorReg = simdNode->GetSingleTempReg(RBM_ALLFLOAT(compiler));
}

// We will first consume the list items in execution (left to right) order,
Expand Down
10 changes: 5 additions & 5 deletions src/coreclr/jit/codegenarmarch.cpp
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Expand Up @@ -2634,7 +2634,7 @@ void CodeGen::genCodeForInitBlkUnroll(GenTreeBlk* node)

if (shouldUse16ByteWideInstrs)
{
const regNumber simdReg = node->GetSingleTempReg(RBM_ALLFLOAT);
const regNumber simdReg = node->GetSingleTempReg(RBM_ALLFLOAT(compiler));

const int initValue = (src->AsIntCon()->IconValue() & 0xFF);
emit->emitIns_R_I(INS_movi, EA_16BYTE, simdReg, initValue, INS_OPTS_16B);
Expand Down Expand Up @@ -2960,8 +2960,8 @@ void CodeGen::genCodeForCpBlkUnroll(GenTreeBlk* node)

if (shouldUse16ByteWideInstrs)
{
const regNumber simdReg1 = node->ExtractTempReg(RBM_ALLFLOAT);
const regNumber simdReg2 = node->GetSingleTempReg(RBM_ALLFLOAT);
const regNumber simdReg1 = node->ExtractTempReg(RBM_ALLFLOAT(compiler));
const regNumber simdReg2 = node->GetSingleTempReg(RBM_ALLFLOAT(compiler));

helper.Unroll(FP_REGSIZE_BYTES, intReg1, simdReg1, simdReg2, srcReg, dstReg, GetEmitter());
}
Expand Down Expand Up @@ -4693,7 +4693,7 @@ void CodeGen::genPushCalleeSavedRegisters()
#endif // DEBUG

#if defined(TARGET_ARM)
regMaskTP maskPushRegsFloat = rsPushRegs & RBM_ALLFLOAT;
regMaskTP maskPushRegsFloat = rsPushRegs & RBM_ALLFLOAT(compiler);
regMaskTP maskPushRegsInt = rsPushRegs & ~maskPushRegsFloat;

maskPushRegsInt |= genStackAllocRegisterMask(compiler->compLclFrameSize, maskPushRegsFloat);
Expand Down Expand Up @@ -4800,7 +4800,7 @@ void CodeGen::genPushCalleeSavedRegisters()

int offset; // This will be the starting place for saving the callee-saved registers, in increasing order.

regMaskTP maskSaveRegsFloat = rsPushRegs & RBM_ALLFLOAT;
regMaskTP maskSaveRegsFloat = rsPushRegs & RBM_ALLFLOAT(compiler);
regMaskTP maskSaveRegsInt = rsPushRegs & ~maskSaveRegsFloat;

#ifdef DEBUG
Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/jit/codegencommon.cpp
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Expand Up @@ -3593,15 +3593,15 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, bool* pXtraRegClobbere
fpAvailMask = RBM_FLT_CALLEE_TRASH(compiler) & ~regArgMaskLive;
if (GlobalJitOptions::compFeatureHfa)
{
fpAvailMask &= RBM_ALLDOUBLE;
fpAvailMask &= RBM_ALLDOUBLE(compiler);
}

if (fpAvailMask == RBM_NONE)
{
fpAvailMask = RBM_ALLFLOAT & ~regArgMaskLive;
fpAvailMask = RBM_ALLFLOAT(compiler) & ~regArgMaskLive;
if (GlobalJitOptions::compFeatureHfa)
{
fpAvailMask &= RBM_ALLDOUBLE;
fpAvailMask &= RBM_ALLDOUBLE(compiler);
}
}

Expand Down Expand Up @@ -5304,7 +5304,7 @@ void CodeGen::genFinalizeFrame()

#if defined(TARGET_ARM)
// TODO-ARM64-Bug?: enable some variant of this for FP on ARM64?
regMaskTP maskPushRegsFloat = maskCalleeRegsPushed & RBM_ALLFLOAT;
regMaskTP maskPushRegsFloat = maskCalleeRegsPushed & RBM_ALLFLOAT(compiler);
regMaskTP maskPushRegsInt = maskCalleeRegsPushed & ~maskPushRegsFloat;

if ((maskPushRegsFloat != RBM_NONE) ||
Expand Down
12 changes: 6 additions & 6 deletions src/coreclr/jit/codegenxarch.cpp
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Expand Up @@ -2869,7 +2869,7 @@ void CodeGen::genCodeForInitBlkUnroll(GenTreeBlk* node)

if (willUseSimdMov)
{
regNumber srcXmmReg = node->GetSingleTempReg(RBM_ALLFLOAT);
regNumber srcXmmReg = node->GetSingleTempReg(RBM_ALLFLOAT(compiler));

unsigned regSize = (size >= YMM_REGSIZE_BYTES) && compiler->compOpportunisticallyDependsOn(InstructionSet_AVX)
? YMM_REGSIZE_BYTES
Expand Down Expand Up @@ -3137,7 +3137,7 @@ void CodeGen::genCodeForCpBlkUnroll(GenTreeBlk* node)

if (size >= XMM_REGSIZE_BYTES)
{
regNumber tempReg = node->GetSingleTempReg(RBM_ALLFLOAT);
regNumber tempReg = node->GetSingleTempReg(RBM_ALLFLOAT(compiler));

instruction simdMov = simdUnalignedMovIns();

Expand Down Expand Up @@ -3459,7 +3459,7 @@ void CodeGen::genStructPutArgUnroll(GenTreePutArgStk* putArgNode)
if (loadSize >= XMM_REGSIZE_BYTES)
#endif
{
xmmTmpReg = putArgNode->GetSingleTempReg(RBM_ALLFLOAT);
xmmTmpReg = putArgNode->GetSingleTempReg(RBM_ALLFLOAT(compiler));
}
if ((loadSize % XMM_REGSIZE_BYTES) != 0)
{
Expand Down Expand Up @@ -7910,13 +7910,13 @@ void CodeGen::genPutArgStkFieldList(GenTreePutArgStk* putArgStk)
intTmpReg = putArgStk->GetSingleTempReg(RBM_ALLINT);
assert(genIsValidIntReg(intTmpReg));
}
if ((rsvdRegs & RBM_ALLFLOAT) != 0)
if ((rsvdRegs & RBM_ALLFLOAT(compiler)) != 0)
{
simdTmpReg = putArgStk->GetSingleTempReg(RBM_ALLFLOAT);
simdTmpReg = putArgStk->GetSingleTempReg(RBM_ALLFLOAT(compiler));
assert(genIsValidFloatReg(simdTmpReg));
}
assert(genCountBits(rsvdRegs) == (unsigned)((intTmpReg == REG_NA) ? 0 : 1) + ((simdTmpReg == REG_NA) ? 0 : 1));
}
}

for (GenTreeFieldList::Use& use : fieldList->Uses())
{
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/jit/hwintrinsiccodegenxarch.cpp
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Expand Up @@ -1527,7 +1527,7 @@ void CodeGen::genAvxOrAvx2Intrinsic(GenTreeHWIntrinsic* node)
regNumber op2Reg = op2->GetRegNum();
regNumber addrBaseReg = REG_NA;
regNumber addrIndexReg = REG_NA;
regNumber maskReg = node->ExtractTempReg(RBM_ALLFLOAT);
regNumber maskReg = node->ExtractTempReg(RBM_ALLFLOAT(compiler));

if (numArgs == 5)
{
Expand Down
23 changes: 7 additions & 16 deletions src/coreclr/jit/lsra.cpp
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Expand Up @@ -693,8 +693,8 @@ LinearScan::LinearScan(Compiler* theCompiler)
availableIntRegs &= ~RBM_FPBASE;
#endif // ETW_EBP_FRAMED

availableFloatRegs = RBM_ALLFLOAT;
availableDoubleRegs = RBM_ALLDOUBLE;
availableFloatRegs = RBM_ALLFLOAT(compiler);
availableDoubleRegs = RBM_ALLDOUBLE(compiler);

#if defined(TARGET_AMD64) || defined(TARGET_ARM64)
if (compiler->opts.compDbgEnC)
Expand All @@ -707,17 +707,6 @@ LinearScan::LinearScan(Compiler* theCompiler)
}
#endif // TARGET_AMD64 || TARGET_ARM64

#if defined(TARGET_AMD64)
// TODO-XARCH-AVX512 switch this to canUseEvexEncoding() once we independetly
// allow EVEX use from the stress flag (currently, if EVEX stress is turned off,
// we cannot use EVEX at all)
if (!compiler->DoJitStressEvexEncoding())
{
availableFloatRegs &= ~RBM_HIGHFLOAT;
availableDoubleRegs &= ~RBM_HIGHFLOAT;
}
#endif

compiler->rpFrameType = FT_NOT_SET;
compiler->rpMustCreateEBPCalled = false;

Expand Down Expand Up @@ -7483,7 +7472,7 @@ regNumber LinearScan::getTempRegForResolution(BasicBlock* fromBlock, BasicBlock*
if (type == TYP_DOUBLE)
{
// Exclude any doubles for which the odd half isn't in freeRegs.
freeRegs = freeRegs & ((freeRegs << 1) & RBM_ALLDOUBLE);
freeRegs = freeRegs & ((freeRegs << 1) & RBM_ALLDOUBLE(this));
}
#endif

Expand Down Expand Up @@ -8985,14 +8974,16 @@ void dumpRegMask(regMaskTP regs)
{
printf("[allIntButFP]");
}
else if (regs == RBM_ALLFLOAT)
/*
else if (regs == RBM_ALLFLOAT(0))
{
printf("[allFloat]");
}
else if (regs == RBM_ALLDOUBLE)
else if (regs == RBM_ALLDOUBLE(0))
{
printf("[allDouble]");
}
*/
else
{
dspRegMask(regs);
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/jit/lsraarmarch.cpp
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Expand Up @@ -811,7 +811,7 @@ int LinearScan::BuildCast(GenTreeCast* cast)
// Floating point to integer casts requires a temporary register.
if (varTypeIsFloating(srcType) && !varTypeIsFloating(castType))
{
buildInternalFloatRegisterDefForNode(cast, RBM_ALLFLOAT);
buildInternalFloatRegisterDefForNode(cast, RBM_ALLFLOAT(compiler));
setInternalRegsDelayFree = true;
}
#endif
Expand Down
6 changes: 3 additions & 3 deletions src/coreclr/jit/lsrabuild.cpp
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Expand Up @@ -2023,7 +2023,7 @@ void LinearScan::UpdateRegStateForStructArg(LclVarDsc* argDsc)

if ((argDsc->GetArgReg() != REG_STK) && (argDsc->GetArgReg() != REG_NA))
{
if (genRegMask(argDsc->GetArgReg()) & (RBM_ALLFLOAT))
if (genRegMask(argDsc->GetArgReg()) & (RBM_ALLFLOAT(compiler)))
{
assert(genRegMask(argDsc->GetArgReg()) & (RBM_FLTARG_REGS));
floatRegState->rsCalleeRegArgMaskLiveIn |= genRegMask(argDsc->GetArgReg());
Expand All @@ -2037,7 +2037,7 @@ void LinearScan::UpdateRegStateForStructArg(LclVarDsc* argDsc)

if ((argDsc->GetOtherArgReg() != REG_STK) && (argDsc->GetOtherArgReg() != REG_NA))
{
if (genRegMask(argDsc->GetOtherArgReg()) & (RBM_ALLFLOAT))
if (genRegMask(argDsc->GetOtherArgReg()) & (RBM_ALLFLOAT(compiler)))
{
assert(genRegMask(argDsc->GetOtherArgReg()) & (RBM_FLTARG_REGS));
floatRegState->rsCalleeRegArgMaskLiveIn |= genRegMask(argDsc->GetOtherArgReg());
Expand Down Expand Up @@ -3859,7 +3859,7 @@ int LinearScan::BuildReturn(GenTree* tree)
break;
case TYP_DOUBLE:
// We ONLY want the valid double register in the RBM_DOUBLERET mask.
useCandidates = (RBM_DOUBLERET & RBM_ALLDOUBLE);
useCandidates = (RBM_DOUBLERET & RBM_ALLDOUBLE(compiler));
break;
case TYP_LONG:
useCandidates = RBM_LNGRET;
Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/jit/targetamd64.h
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Expand Up @@ -78,11 +78,11 @@
#endif // !UNIX_AMD64_ABI
#define CSE_CONSTS 1 // Enable if we want to CSE constants

#define RBM_ALLFLOAT (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM3 | RBM_XMM4 | RBM_XMM5 | RBM_XMM6 | RBM_XMM7 | RBM_XMM8 | RBM_XMM9 | RBM_XMM10 | RBM_XMM11 | RBM_XMM12 | RBM_XMM13 | RBM_XMM14 | RBM_XMM15 | RBM_XMM16 | RBM_XMM17 | RBM_XMM18 | RBM_XMM19 | RBM_XMM20 | RBM_XMM21 | RBM_XMM22 | RBM_XMM23 | RBM_XMM24 | RBM_XMM25 | RBM_XMM26 | RBM_XMM27 | RBM_XMM28 | RBM_XMM29 | RBM_XMM30 | RBM_XMM31)
#define RBM_LOWFLOAT (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM3 | RBM_XMM4 | RBM_XMM5 | RBM_XMM6 | RBM_XMM7 | RBM_XMM8 | RBM_XMM9 | RBM_XMM10 | RBM_XMM11 | RBM_XMM12 | RBM_XMM13 | RBM_XMM14 | RBM_XMM15 )
#define RBM_HIGHFLOAT (RBM_XMM16 | RBM_XMM17 | RBM_XMM18 | RBM_XMM19 | RBM_XMM20 | RBM_XMM21 | RBM_XMM22 | RBM_XMM23 | RBM_XMM24 | RBM_XMM25 | RBM_XMM26 | RBM_XMM27 | RBM_XMM28 | RBM_XMM29 | RBM_XMM30 | RBM_XMM31)
#define RBM_ALLFLOAT(c) ((c->DoJitStressEvexEncoding()) ? RBM_LOWFLOAT | RBM_HIGHFLOAT : RBM_LOWFLOAT)

#define RBM_ALLDOUBLE RBM_ALLFLOAT
#define RBM_ALLDOUBLE(c) RBM_ALLFLOAT(c)
#define REG_FP_FIRST REG_XMM0
#define REG_FP_LAST REG_XMM31
#define FIRST_FP_ARGREG REG_XMM0
Expand Down Expand Up @@ -225,8 +225,8 @@
#define CNT_CALLEE_TRASH (7)
#define CNT_CALLEE_ENREG (CNT_CALLEE_SAVED)

#define CNT_CALLEE_SAVED_FLOAT (6)
#define CNT_CALLEE_TRASH_FLOAT (26)
#define CNT_CALLEE_SAVED_FLOAT (10)
#define CNT_CALLEE_TRASH_FLOAT (22)

#define REG_CALLEE_SAVED_ORDER REG_EBX,REG_ESI,REG_EDI,REG_ETW_FRAMED_EBP_LIST REG_R12,REG_R13,REG_R14,REG_R15
#define RBM_CALLEE_SAVED_ORDER RBM_EBX,RBM_ESI,RBM_EDI,RBM_ETW_FRAMED_EBP_LIST RBM_R12,RBM_R13,RBM_R14,RBM_R15
Expand Down
6 changes: 3 additions & 3 deletions src/coreclr/jit/targetarm.h
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Expand Up @@ -71,8 +71,8 @@
#define RBM_DEFAULT_HELPER_CALL_TARGET RBM_R12

#define RBM_ALLINT (RBM_INT_CALLEE_SAVED | RBM_INT_CALLEE_TRASH)
#define RBM_ALLFLOAT (RBM_FLT_CALLEE_SAVED | RBM_FLT_CALLEE_TRASH(__noop))
#define RBM_ALLDOUBLE (RBM_F0|RBM_F2|RBM_F4|RBM_F6|RBM_F8|RBM_F10|RBM_F12|RBM_F14|RBM_F16|RBM_F18|RBM_F20|RBM_F22|RBM_F24|RBM_F26|RBM_F28|RBM_F30)
#define RBM_ALLFLOAT(c) (RBM_FLT_CALLEE_SAVED | RBM_FLT_CALLEE_TRASH(__noop))
#define RBM_ALLDOUBLE(c) (RBM_F0|RBM_F2|RBM_F4|RBM_F6|RBM_F8|RBM_F10|RBM_F12|RBM_F14|RBM_F16|RBM_F18|RBM_F20|RBM_F22|RBM_F24|RBM_F26|RBM_F28|RBM_F30)

#define REG_VAR_ORDER REG_R3,REG_R2,REG_R1,REG_R0,REG_R4,REG_LR,REG_R12,\
REG_R5,REG_R6,REG_R7,REG_R8,REG_R9,REG_R10
Expand Down Expand Up @@ -284,7 +284,7 @@

#define RBM_ARG_REGS (RBM_ARG_0|RBM_ARG_1|RBM_ARG_2|RBM_ARG_3)
#define RBM_FLTARG_REGS (RBM_F0|RBM_F1|RBM_F2|RBM_F3|RBM_F4|RBM_F5|RBM_F6|RBM_F7|RBM_F8|RBM_F9|RBM_F10|RBM_F11|RBM_F12|RBM_F13|RBM_F14|RBM_F15)
#define RBM_DBL_REGS RBM_ALLDOUBLE
#define RBM_DBL_REGS RBM_ALLDOUBLE(0)

extern const regNumber fltArgRegs [MAX_FLOAT_REG_ARG];
extern const regMaskTP fltArgMasks[MAX_FLOAT_REG_ARG];
Expand Down
4 changes: 2 additions & 2 deletions src/coreclr/jit/targetarm64.h
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Expand Up @@ -79,8 +79,8 @@
#define RBM_DEFAULT_HELPER_CALL_TARGET RBM_R12

#define RBM_ALLINT (RBM_INT_CALLEE_SAVED | RBM_INT_CALLEE_TRASH)
#define RBM_ALLFLOAT (RBM_FLT_CALLEE_SAVED | RBM_FLT_CALLEE_TRASH(__noop))
#define RBM_ALLDOUBLE RBM_ALLFLOAT
#define RBM_ALLFLOAT(c) (RBM_FLT_CALLEE_SAVED | RBM_FLT_CALLEE_TRASH(__noop))
#define RBM_ALLDOUBLE(c) RBM_ALLFLOAT(c)

// REG_VAR_ORDER is: (CALLEE_TRASH & ~CALLEE_TRASH_NOGC), CALLEE_TRASH_NOGC, CALLEE_SAVED
#define REG_VAR_ORDER REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, \
Expand Down
6 changes: 3 additions & 3 deletions src/coreclr/jit/targetx86.h
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Expand Up @@ -88,13 +88,13 @@

#define RBM_FLTARG_REGS (RBM_FLTARG_0|RBM_FLTARG_1|RBM_FLTARG_2|RBM_FLTARG_3)

#define RBM_ALLFLOAT (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM3 | RBM_XMM4 | RBM_XMM5 | RBM_XMM6 | RBM_XMM7)
#define RBM_ALLDOUBLE RBM_ALLFLOAT
#define RBM_ALLFLOAT(c) (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM3 | RBM_XMM4 | RBM_XMM5 | RBM_XMM6 | RBM_XMM7)
#define RBM_ALLDOUBLE(c) RBM_ALLFLOAT(c)

// TODO-CQ: Currently we are following the x86 ABI for SSE2 registers.
// This should be reconsidered.
#define RBM_FLT_CALLEE_SAVED RBM_NONE
#define RBM_FLT_CALLEE_TRASH(c) RBM_ALLFLOAT
#define RBM_FLT_CALLEE_TRASH(c) RBM_ALLFLOAT(c)
#define REG_VAR_ORDER_FLT REG_XMM0, REG_XMM1, REG_XMM2, REG_XMM3, REG_XMM4, REG_XMM5, REG_XMM6, REG_XMM7

#define REG_FLT_CALLEE_SAVED_FIRST REG_XMM6
Expand Down
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