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Arm64: Implement VectorTableLookup/VectorTableLookupExtension intrinsinsic + Consecutive registers support #80297
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…nsecutiveRegistersFree()
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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@@ -56,27 +56,19 @@ RefPosition* LinearScan::getNextConsecutiveRefPosition(RefPosition* refPosition) | |
| // firstRefPosition - First refPosition of the series of consecutive registers. | ||
| // firstRegAssigned - Register assigned to the first refposition. | ||
|
||
| // | ||
| // Returns: | ||
| // True if all the consecutive registers starting from `firstRegAssigned` were free. Even if one | ||
| // of them is busy, returns false and does not change the registerAssignment of any refPositions. | ||
| // Note: | ||
| // This method will set the registerAssignment of subsequent RefPositions with consecutive registers. | ||
| // Some of the registers could be busy, and they will be spilled. We would end up with busy registers if | ||
| // we did not find free consecutive registers. | ||
| // | ||
| bool LinearScan::setNextConsecutiveRegisterAssignment(RefPosition* firstRefPosition, regNumber firstRegAssigned) | ||
| void LinearScan::setNextConsecutiveRegisterAssignment(RefPosition* firstRefPosition, regNumber firstRegAssigned) | ||
| { | ||
| assert(compiler->info.needsConsecutiveRegisters); | ||
| assert(firstRefPosition->assignedReg() == firstRegAssigned); | ||
| assert(isSingleRegister(genRegMask(firstRegAssigned))); | ||
| assert(firstRefPosition->isFirstRefPositionOfConsecutiveRegisters()); | ||
| assert(emitter::isVectorRegister(firstRegAssigned)); | ||
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| // Verify that all the consecutive registers needed are free, if not, return false. | ||
| // Need to do this before we set registerAssignment of any of the refPositions that | ||
| // are part of the range. | ||
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| if (!areNextConsecutiveRegistersFree(firstRegAssigned, firstRefPosition->regCount, | ||
| firstRefPosition->getInterval()->registerType)) | ||
| { | ||
| return false; | ||
| } | ||
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| RefPosition* consecutiveRefPosition = getNextConsecutiveRefPosition(firstRefPosition); | ||
| regNumber regToAssign = firstRegAssigned == REG_FP_LAST ? REG_FP_FIRST : REG_NEXT(firstRegAssigned); | ||
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@@ -114,8 +106,6 @@ bool LinearScan::setNextConsecutiveRegisterAssignment(RefPosition* firstRefPosit | |
| } | ||
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| assert(refPosCount == firstRefPosition->regCount); | ||
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| return true; | ||
| } | ||
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| //------------------------------------------------------------------------ | ||
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