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[mono][interp] Add instrinsics for common Vector128 operations #81782

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Merged
BrzVlad merged 9 commits into from
Feb 28, 2023
Merged

[mono][interp] Add instrinsics for common Vector128 operations #81782

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c439344
[mono][interp] Move defines from transform.c
BrzVlad Jan 9, 2023
d4eb2aa
[mono][interp] Move more defines from transform.c
BrzVlad Jan 9, 2023
7e4a385
[mono][interp] Add intrinsics for most common V128 operations
BrzVlad Dec 2, 2022
d42c15c
[mono][interp] Add option to disable simd intrinsics
BrzVlad Feb 7, 2023
f69a049
[mono][interp] Disable simd intrinsics by default on wasm
BrzVlad Feb 7, 2023
db74dd5
[mono][interp] Replace v128_create with v128_ldc if possible
BrzVlad Feb 7, 2023
8ffac07
[mono][interp] Remove op_Division
BrzVlad Feb 9, 2023
629cd94
[mono][interp] Don't emit intrinsics for unsupported vector types
BrzVlad Feb 13, 2023
719523d
[mono][interp] Vector extensions used in these intrinsics are a GNUC …
BrzVlad Feb 13, 2023
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[mono][interp] Remove op_Division 
It is actually not used in bcl, it is not really vectorized on any platforms and the codegen for the interp implementation is massive and inefficient.
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@BrzVlad
BrzVlad committed Feb 21, 2023
commit 8ffac0787d3c6a71bd6f8ae08c2c11861e970c51
7 changes: 0 additions & 7 deletions src/mono/mono/mini/interp/interp-simd-intrins.def
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Original file line number Diff line number Diff line change
Expand Up @@ -9,13 +9,6 @@ INTERP_SIMD_INTRINSIC_P_PP (INTERP_SIMD_INTRINSIC_V128_I4_SUB, interp_v128_i4_op
INTERP_SIMD_INTRINSIC_P_PP (INTERP_SIMD_INTRINSIC_V128_BITWISE_AND, interp_v128_op_bitwise_and)
INTERP_SIMD_INTRINSIC_P_PP (INTERP_SIMD_INTRINSIC_V128_BITWISE_OR, interp_v128_op_bitwise_or)

INTERP_SIMD_INTRINSIC_P_PP (INTERP_SIMD_INTRINSIC_V128_I1_DIVISION, interp_v128_i1_op_division)
INTERP_SIMD_INTRINSIC_P_PP (INTERP_SIMD_INTRINSIC_V128_U1_DIVISION, interp_v128_u1_op_division)
INTERP_SIMD_INTRINSIC_P_PP (INTERP_SIMD_INTRINSIC_V128_I2_DIVISION, interp_v128_i2_op_division)
INTERP_SIMD_INTRINSIC_P_PP (INTERP_SIMD_INTRINSIC_V128_U2_DIVISION, interp_v128_u2_op_division)
INTERP_SIMD_INTRINSIC_P_PP (INTERP_SIMD_INTRINSIC_V128_I4_DIVISION, interp_v128_i4_op_division)
INTERP_SIMD_INTRINSIC_P_PP (INTERP_SIMD_INTRINSIC_V128_U4_DIVISION, interp_v128_u4_op_division)

INTERP_SIMD_INTRINSIC_P_PP (INTERP_SIMD_INTRINSIC_V128_BITWISE_EQUALITY, interp_v128_op_bitwise_equality)
INTERP_SIMD_INTRINSIC_P_PP (INTERP_SIMD_INTRINSIC_V128_BITWISE_INEQUALITY, interp_v128_op_bitwise_inequality)

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37 changes: 0 additions & 37 deletions src/mono/mono/mini/interp/interp-simd.c
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Expand Up @@ -72,43 +72,6 @@ interp_v128_op_bitwise_or (gpointer res, gpointer v1, gpointer v2)
*(v128_i4*)res = *(v128_i4*)v1 | *(v128_i4*)v2;
}

// op_Division
static void
interp_v128_i1_op_division (gpointer res, gpointer v1, gpointer v2)
{
*(v128_i1*)res = *(v128_i1*)v1 / *(v128_i1*)v2;
}

static void
interp_v128_u1_op_division (gpointer res, gpointer v1, gpointer v2)
{
*(v128_u1*)res = *(v128_u1*)v1 / *(v128_u1*)v2;
}

static void
interp_v128_i2_op_division (gpointer res, gpointer v1, gpointer v2)
{
*(v128_i2*)res = *(v128_i2*)v1 / *(v128_i2*)v2;
}

static void
interp_v128_u2_op_division (gpointer res, gpointer v1, gpointer v2)
{
*(v128_u2*)res = *(v128_u2*)v1 / *(v128_u2*)v2;
}

static void
interp_v128_i4_op_division (gpointer res, gpointer v1, gpointer v2)
{
*(v128_i4*)res = *(v128_i4*)v1 / *(v128_i4*)v2;
}

static void
interp_v128_u4_op_division (gpointer res, gpointer v1, gpointer v2)
{
*(v128_u4*)res = *(v128_u4*)v1 / *(v128_u4*)v2;
}

// op_Equality
static void
interp_v128_op_bitwise_equality (gpointer res, gpointer v1, gpointer v2)
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1 change: 0 additions & 1 deletion src/mono/mono/mini/interp/simd-methods.def
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Expand Up @@ -7,7 +7,6 @@ SIMD_METHOD(get_Zero)
SIMD_METHOD(op_Addition)
SIMD_METHOD(op_BitwiseAnd)
SIMD_METHOD(op_BitwiseOr)
SIMD_METHOD(op_Division)
SIMD_METHOD(op_Equality)
SIMD_METHOD(op_ExclusiveOr)
SIMD_METHOD(op_Explicit)
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11 changes: 0 additions & 11 deletions src/mono/mono/mini/interp/transform-simd.c
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Expand Up @@ -72,7 +72,6 @@ static guint16 sri_vector128_t_methods [] = {
SN_op_Addition,
SN_op_BitwiseAnd,
SN_op_BitwiseOr,
SN_op_Division,
SN_op_Equality,
SN_op_ExclusiveOr,
SN_op_Inequality,
Expand Down Expand Up @@ -349,16 +348,6 @@ emit_sri_vector128_t (TransformData *td, MonoMethod *cmethod, MonoMethodSignatur
simd_opcode = MINT_SIMD_INTRINS_P_PP;
simd_intrins = INTERP_SIMD_INTRINSIC_V128_BITWISE_OR;
break;
case SN_op_Division:
g_assert (scalar_arg == -1);
simd_opcode = MINT_SIMD_INTRINS_P_PP;
if (atype == MONO_TYPE_I1) simd_intrins = INTERP_SIMD_INTRINSIC_V128_I1_DIVISION;
else if (atype == MONO_TYPE_U1) simd_intrins = INTERP_SIMD_INTRINSIC_V128_U1_DIVISION;
else if (atype == MONO_TYPE_I2) simd_intrins = INTERP_SIMD_INTRINSIC_V128_I2_DIVISION;
else if (atype == MONO_TYPE_U2) simd_intrins = INTERP_SIMD_INTRINSIC_V128_U2_DIVISION;
else if (atype == MONO_TYPE_I4) simd_intrins = INTERP_SIMD_INTRINSIC_V128_I4_DIVISION;
else if (atype == MONO_TYPE_U4) simd_intrins = INTERP_SIMD_INTRINSIC_V128_U4_DIVISION;
break;
case SN_op_Equality:
if (atype != MONO_TYPE_R4 && atype != MONO_TYPE_R8) {
simd_opcode = MINT_SIMD_INTRINS_P_PP;
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