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Adding support for Vector512 Equals, EqualsAny, op_Equality, and op_Inequality. #83470

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Merged
tannergooding merged 18 commits into from
Apr 10, 2023
Merged

Adding support for Vector512 Equals, EqualsAny, op_Equality, and op_Inequality. #83470

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029ceb9
Implement `Vector512.Equals` by way of special `AVX512` intrinsic.
DeepakRajendrakumaran Mar 27, 2023
4926d87
Add Vector512 `Equals`, `EqualsAll/op_Equality` `op_Inequality`.
DeepakRajendrakumaran Mar 28, 2023
a18a9ee
Fix `vpmovm2x` instructions for `MoveMaskToVectorSpecial`.
anthonycanino Mar 16, 2023
0bf15f8
Move `Vector512` Equals into `gtNewSimdCmpOpNode`.
anthonycanino Mar 16, 2023
eaa9843
Adds `EqualsAny`.
anthonycanino Mar 16, 2023
adc99b3
Fix `kortestq` and `kortestd` opcode gen (W bit).
anthonycanino Mar 21, 2023
64bc6b6
Fix merge and update instr flags.
DeepakRajendrakumaran Mar 28, 2023
21e545a
Addressing review comments.
DeepakRajendrakumaran Mar 28, 2023
dece3cc
Removing unnecessary files.
DeepakRajendrakumaran Mar 28, 2023
65aaba3
Addressing review comments.
DeepakRajendrakumaran Apr 5, 2023
4caa9d0
Fixing bug.
DeepakRajendrakumaran Apr 5, 2023
54f27a1
Fixing k reg display on x86.
DeepakRajendrakumaran Apr 6, 2023
3d4dc45
Merge pull request #13 from DeepakRajendrakumaran/Anthony_Eq
anthonycanino Apr 6, 2023
27e46cd
Setting Resets_ZF to right value.
DeepakRajendrakumaran Apr 6, 2023
ea63007
Fixing extract.
DeepakRajendrakumaran Apr 7, 2023
8f54124
Merge pull request #14 from DeepakRajendrakumaran/AnthonyEq
anthonycanino Apr 7, 2023
5ed9516
Merge remote-tracking branch 'dotnet/main' into avx512-equality
tannergooding Apr 9, 2023
411bfa4
Merge remote-tracking branch 'origin/main' into avx512-equality
tannergooding Apr 10, 2023
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Removing unnecessary files.
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@DeepakRajendrakumaran
DeepakRajendrakumaran committed Apr 5, 2023
commit dece3ccf44986d243aa9adf32b6850b6fc5067c9
100 changes: 0 additions & 100 deletions 0001-Changes-for-AVX_512_add.patch
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15 changes: 14 additions & 1 deletion src/coreclr/jit/emitxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ bool emitter::IsSSEOrAVXInstruction(instruction ins)
// ins - The instruction to check.
//
// Returns:
// `true` if this instruction require K register.
// `true` if this instruction requires K register.
//
bool emitter::IsKInstruction(instruction ins)
{
Expand Down Expand Up @@ -253,6 +253,19 @@ bool emitter::IsDstSrcSrcAVXInstruction(instruction ins) const
return (flags & INS_Flags_IsDstSrcSrcAVXInstruction) != 0;
}

// Returns true if the AVX instruction requires 3 operands and writes result
// to mask register.
bool emitter::IsThreeOperandInstructionMask(instruction ins) const
{
if (!UseSimdEncoding())
{
return false;
}
Comment on lines +258 to +261
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@tannergooding tannergooding Mar 29, 2023

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Don't expect you to do this here, since this is consistent with the other methods.

But I think we can in general simplify this and several of the other SIMD only flags to something like:

insFlags flags = CodeGenInterface::instInfo[ins];

if ((flags & INS_Flags_Is3OperandInstructionMask) != 0)
{
    assert(UseSimdEncoding());
    return true;
}

return false;

The UseSimdEncoding() is itself a flag check now and we should never be setting these SIMD only flags on non-SIMD instructions.

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@tannergooding tannergooding Mar 29, 2023

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I'll log an issue for us to look at that as a cleanup item in some follow up PR.


insFlags flags = CodeGenInterface::instInfo[ins];
return (flags & INS_Flags_Is3OperandInstructionMask) != 0;
}

//------------------------------------------------------------------------
// HasRegularWideForm: Many x86/x64 instructions follow a regular encoding scheme where the
// byte-sized version of an instruction has the lowest bit of the opcode cleared
Expand Down
1 change: 1 addition & 0 deletions src/coreclr/jit/emitxarch.h
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Expand Up @@ -402,6 +402,7 @@ void SetContains256bitOrMoreAVX(bool value)

bool IsDstDstSrcAVXInstruction(instruction ins) const;
bool IsDstSrcSrcAVXInstruction(instruction ins) const;
bool IsThreeOperandInstructionMask(instruction ins) const;
static bool HasRegularWideForm(instruction ins);
static bool HasRegularWideImmediateForm(instruction ins);
static bool DoesWriteZeroFlag(instruction ins);
Expand Down
29 changes: 15 additions & 14 deletions src/coreclr/jit/instr.h
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Expand Up @@ -141,37 +141,38 @@ enum insFlags : uint64_t
// Avx
INS_Flags_IsDstDstSrcAVXInstruction = 1ULL << 25,
INS_Flags_IsDstSrcSrcAVXInstruction = 1ULL << 26,
INS_Flags_Is3OperandInstructionMask = 1ULL << 27,

// w and s bits
INS_FLAGS_Has_Wbit = 1ULL << 27,
INS_FLAGS_Has_Sbit = 1ULL << 28,
INS_FLAGS_Has_Wbit = 1ULL << 28,
INS_FLAGS_Has_Sbit = 1ULL << 29,

// instruction input size
// if not input size is set, instruction defaults to using
// the emitAttr for size
Input_8Bit = 1ULL << 29,
Input_16Bit = 1ULL << 30,
Input_32Bit = 1ULL << 31,
Input_64Bit = 1ULL << 32,
Input_Mask = (0xFULL) << 29,
Input_8Bit = 1ULL << 30,
Input_16Bit = 1ULL << 31,
Input_32Bit = 1ULL << 32,
Input_64Bit = 1ULL << 33,
Input_Mask = (0xFULL) << 30,

// encoding of the REX.W-bit
REX_W0 = 1ULL << 33,
REX_W1 = 1ULL << 34,
REX_WX = 1ULL << 35,
REX_W0 = 1ULL << 34,
REX_W1 = 1ULL << 35,
REX_WX = 1ULL << 36,

// encoding of the REX.W-bit is considered for EVEX only and W0 or WIG otherwise
REX_W0_EVEX = REX_W0,
REX_W1_EVEX = 1ULL << 36,
REX_W1_EVEX = 1ULL << 37,

// encoding of the REX.W-bit is ignored
REX_WIG = REX_W0,

// whether VEX or EVEX encodings are directly supported
Encoding_VEX = 1ULL << 37,
Encoding_EVEX = 1ULL << 38,
Encoding_VEX = 1ULL << 38,
Encoding_EVEX = 1ULL << 39,

KInstruction = 1ULL << 39,
KInstruction = 1ULL << 40,

// Listed above so it is "inline" with the other Resets_* flags
// Resets_ZF = 1ULL << 39,
Expand Down
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