Skip to content

Update handling of limited register during consecutive registers allocation #84588

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
kunalspathak merged 12 commits into from
Apr 11, 2023
Merged

Update handling of limited register during consecutive registers allocation #84588

Changes from 1 commit
Commits
Show all changes
12 commits
Select commit Hold shift + click to select a range
d452147
Fix issue to handle candidates that don't have assignedInterval in sp…
kunalspathak Apr 9, 2023
1708964
Do not let limitRegs reduce the number of candidates
kunalspathak Apr 10, 2023
c31cfbd
getConsecutiveCandidates update if freeCandidate=RBM_NONE
kunalspathak Apr 10, 2023
e684275
Relax limitStressRegs for refpositions live at consecutive register p…
kunalspathak Apr 10, 2023
13e85ac
Update minRegCount for registerAssignment
kunalspathak Apr 10, 2023
f2cda1e
Remove LsraLimitFPSetForConsecutive
kunalspathak Apr 10, 2023
c0c3f4a
Added an assert
kunalspathak Apr 10, 2023
01ec812
misc changes
kunalspathak Apr 10, 2023
e5698cc
jit format
kunalspathak Apr 11, 2023
fe4f675
Merge remote-tracking branch 'origin/main' into consecutive_jitstress…
kunalspathak Apr 11, 2023
2a3d0f2
Use BitOperations::BitScanForward()
kunalspathak Apr 11, 2023
3f5dfd7
review feedback
kunalspathak Apr 11, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Prev Previous commit
Next Next commit
jit format
  • Loading branch information
@kunalspathak
kunalspathak committed Apr 11, 2023
commit e5698ccebce1d7be859d2465a43e37574f81e555
10 changes: 5 additions & 5 deletions src/coreclr/jit/lsra.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -655,7 +655,7 @@ LinearScan::LinearScan(Compiler* theCompiler)
firstColdLoc = MaxLocation;

#ifdef DEBUG
maxNodeLocation = 0;
maxNodeLocation = 0;
consecutiveRegistersLocation = 0;

activeRefPosition = nullptr;
Expand Down Expand Up @@ -11696,8 +11696,8 @@ void LinearScan::RegisterSelection::try_SPILL_COST()
Interval* assignedInterval = spillCandidateRegRecord->assignedInterval;
RefPosition* recentRefPosition = assignedInterval != nullptr ? assignedInterval->recentRefPosition : nullptr;

// Can and should the interval in this register be spilled for this one,
// if we don't find a better alternative?
// Can and should the interval in this register be spilled for this one,
// if we don't find a better alternative?

weight_t currentSpillWeight = 0;
#ifdef TARGET_ARM64
Expand Down Expand Up @@ -12072,7 +12072,7 @@ regMaskTP LinearScan::RegisterSelection::select(Interval* currentInterval,
// If a method has consecutive registers and we are assigning to refPositions that are not part
// of consecutive registers, but are live at same location, skip the limit stress for them, because
// there are high chances that many registers are busy for consecutive requirements and we don't
// have enough remaining for other refpositions (like operands).
// have enough remaining for other refpositions (like operands).
}
else
#endif
Expand Down Expand Up @@ -12340,7 +12340,7 @@ regMaskTP LinearScan::RegisterSelection::select(Interval* currentInterval,
// is the number of consecutive registers needed.
// Remove the `inUseOrBusyRegsMask` from the original candidates list and find one
// such range that is consecutive. Next, append that range to the `candidates`.
//
//
regMaskTP limitCandidatesForConsecutive = refPosition->registerAssignment & inUseOrBusyRegsMask;
regMaskTP overallLimitCandidates;
regMaskTP limitConsecutiveResult =
Expand Down