Introduce isLiveAtConsecutiveRegistersLoc and fix #84747

This method will track if the defs/uses are live at the same location as
where the consecutive registers were allocated. If yes, it will skip the
constraint imposition on it during JitStressRegs

src/coreclr/jit/lsra.cpp

@@ -12087,12 +12087,13 @@ regMaskTP LinearScan::RegisterSelection::select(Interval*    currentInterval,
 
 #ifdef DEBUG
 #ifdef TARGET_ARM64
-    if (!refPosition->needsConsecutive && (linearScan->consecutiveRegistersLocation == refPosition->nodeLocation))
+    if (!refPosition->needsConsecutive && refPosition->isLiveAtConsecutiveRegistersLoc(linearScan->consecutiveRegistersLocation))
     {
         // If a method has consecutive registers and we are assigning to refPositions that are not part
-        // of consecutive registers, but are live at same location, skip the limit stress for them, because
-        // there are high chances that many registers are busy for consecutive requirements and we don't
-        // have enough remaining for other refpositions (like operands).
+        // of consecutive registers, but are live at the same location, skip the limit stress for them,
+        // because there are high chances that many registers are busy for consecutive requirements and
+        // we do not have enough remaining for other refpositions (like operands). Likewise, skip for the
+        // definition node that comes after that, for which, all the registers are in "delayRegFree" state.
     }
     else
 #endif

src/coreclr/jit/lsra.h

@@ -2652,6 +2652,10 @@ class RefPosition
         }
         return false;
     }
+
+#ifdef DEBUG
+    bool isLiveAtConsecutiveRegistersLoc(LsraLocation consecutiveRegistersLocation);
+#endif
 #endif // TARGET_ARM64
 
 #ifdef DEBUG

src/coreclr/jit/lsraarm64.cpp

@@ -1802,6 +1802,45 @@ int LinearScan::BuildConsecutiveRegistersForUse(GenTree* treeNode, GenTree* rmwN
 
     return srcCount;
 }
+
+#ifdef DEBUG
+//------------------------------------------------------------------------
+// isLiveAtConsecutiveRegistersLoc: Check if the refPosition is live at the location
+//    where consecutive registers are needed. This is used during JitStressRegs to
+//    not constrained the register requirements for such refpositions, because lot
+//    of registers will be busy. For RefTypeUse, it will just see if the nodeLocation
+//    matches with the tracking `consecutiveRegistersLocation`. For Def, it will check
+//    the underlying `GenTree*` to see if the tree that produced it had consecutive
+//    registers requirement.
+// 
+//
+// Arguments:
+//    consecutiveRegistersLocation - The most recent location where consecutive
+//     registers were needed.
+//
+bool RefPosition::isLiveAtConsecutiveRegistersLoc(LsraLocation consecutiveRegistersLocation)
+{
+    if (needsConsecutive)
+    {
+        return true;
+    }
+
+    if (refType == RefTypeDef)
+    {
+        if (treeNode->OperIsHWIntrinsic())
+        {
+            const HWIntrinsic intrin(treeNode->AsHWIntrinsic());
+            return HWIntrinsicInfo::NeedsConsecutiveRegisters(intrin.id);
+        }
+    }
+    else if ((refType == RefTypeUse) || (refType == RefTypeUpperVectorRestore))
+    {
+        return consecutiveRegistersLocation == nodeLocation;
+    }
+    return false;
+}
+#endif
+
 #endif
 
 #endif // TARGET_ARM64

src/coreclr/jit/lsrabuild.cpp

@@ -423,7 +423,13 @@ void LinearScan::checkConflictingDefUse(RefPosition* useRP)
     {
         if (!isSingleRegister(newAssignment) || !theInterval->hasInterferingUses)
         {
-            defRP->registerAssignment = newAssignment;
+#ifdef TARGET_ARM64
+            if (!compiler->info.compNeedsConsecutiveRegisters ||
+                !defRP->isLiveAtConsecutiveRegistersLoc(consecutiveRegistersLocation))
+#endif
+            {
+                defRP->registerAssignment = newAssignment;
+            }
         }
     }
     else
@@ -1808,7 +1814,9 @@ void LinearScan::buildRefPositionsForNode(GenTree* tree, LsraLocation currentLoc
 #ifdef TARGET_ARM64
                 else if (newRefPosition->needsConsecutive)
                 {
+#if FEATURE_PARTIAL_SIMD_CALLEE_SAVE
                     assert(newRefPosition->refType == RefTypeUpperVectorRestore);
+#endif
                     minRegCount++;
                 }
 #endif