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[Mono][RISC-V] emit mul inst instead of emulated mul #85445

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Merged
vargaz merged 23 commits into from
Jul 8, 2023
Merged

[Mono][RISC-V] emit mul inst instead of emulated mul #85445

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24a076e
update makefile
Xinlong-Wu Mar 20, 2023
563fb82
add format file
Xinlong-Wu Apr 3, 2023
cfa721e
use mul inst instead of emulate mul
Xinlong-Wu Apr 4, 2023
16bb00a
emit get_throw_trampoline
Xinlong-Wu Apr 5, 2023
b461b98
mono_riscv_throw_exception
Xinlong-Wu Apr 5, 2023
c44f58d
fix error of stack trace
Xinlong-Wu Apr 5, 2023
0d83ad8
test case
Xinlong-Wu Apr 8, 2023
bd379d6
output inst idiv
Xinlong-Wu Apr 8, 2023
8d26d93
implement mono_arch_get_throw_corlib_exception
Xinlong-Wu Apr 8, 2023
31d99e4
fix rdiv
Xinlong-Wu Apr 9, 2023
2930696
move ArgOnStack arg at prologue
Xinlong-Wu Apr 10, 2023
d47bf35
fix emit_imm
Xinlong-Wu Apr 11, 2023
053f246
test imm
Xinlong-Wu Apr 11, 2023
3f59f4d
update test case
Xinlong-Wu Apr 12, 2023
6fe9c02
Merge branch 'riscv-jit-rv64' of github.com:Xinlong-Wu/runtime into r…
Xinlong-Wu Apr 12, 2023
1dc76d0
use swich to process return value
Xinlong-Wu Apr 14, 2023
6032d21
fix offset of params in a call
Xinlong-Wu Apr 16, 2023
b1057d3
lowering OP_IDIV_IMM
Xinlong-Wu Apr 16, 2023
5c48e11
fmt
Xinlong-Wu Apr 27, 2023
85edadf
remove test file
Xinlong-Wu Apr 27, 2023
1b170bc
Merge branch 'dotnet:main' into pr-Apr
Xinlong-Wu Apr 27, 2023
265c8c6
address comment
Xinlong-Wu May 4, 2023
fbc69c8
Merge branch 'pr-Apr' of github.com:Xinlong-Wu/runtime into pr-Apr
Xinlong-Wu May 4, 2023
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implement mono_arch_get_throw_corlib_exception
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@Xinlong-Wu
Xinlong-Wu committed Apr 8, 2023
commit 8d26d93d4994abffd933b93e2030fbd49090e73e
10 changes: 5 additions & 5 deletions src/mono/mono/mini/cpu-riscv64.mdesc
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Original file line number Diff line number Diff line change
Expand Up @@ -177,11 +177,11 @@ riscv_bge: src1:i src2:i len:8
riscv_bgeu: src1:i src2:i len:8
riscv_blt: src1:i src2:i len:8
riscv_bltu: src1:i src2:i len:8
riscv_exc_beq: src1:i src2:i len:8
riscv_exc_bne: src1:i src2:i len:8
riscv_exc_bgeu: src1:i src2:i len:8
riscv_exc_blt: src1:i src2:i len:8
riscv_exc_bltu: src1:i src2:i len:8
riscv_exc_beq: src1:i src2:i len:12
riscv_exc_bne: src1:i src2:i len:12
riscv_exc_bgeu: src1:i src2:i len:12
riscv_exc_blt: src1:i src2:i len:12
riscv_exc_bltu: src1:i src2:i len:12
riscv_slt: dest:i src1:i src2:i len:4
riscv_sltu: dest:i src1:i src2:i len:4
riscv_slti: dest:i src1:i len:4
Expand Down
13 changes: 8 additions & 5 deletions src/mono/mono/mini/exceptions-riscv.c
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Expand Up @@ -154,7 +154,8 @@ get_throw_trampoline (int size, gboolean corlib, gboolean rethrow, gboolean llvm
/* Save gregs */
code = mono_riscv_emit_store_stack (code, 0xffffffff, RISCV_FP, -gregs_offset, FALSE);
if (corlib && !llvm)
NOT_IMPLEMENTED;
/* The real ra is in A1 */
code = mono_riscv_emit_store (code, RISCV_A1, RISCV_FP, -gregs_offset + (RISCV_RA * sizeof(host_mgreg_t)), 0);

/* Save previous fp/sp */
code = mono_riscv_emit_load (code, RISCV_T0, RISCV_FP, -2 * sizeof(host_mgreg_t), 0);
Expand All @@ -170,8 +171,11 @@ get_throw_trampoline (int size, gboolean corlib, gboolean rethrow, gboolean llvm
/* Arg1 = exception object/type token */
// riscv_addi (code, RISCV_A0, RISCV_A0, 0);
/* Arg2 = caller ip, should be return address in this case */
if (corlib)
NOT_IMPLEMENTED;
if (corlib){
// caller ip are set to A1 already
if (llvm)
NOT_IMPLEMENTED;
}
else
code = mono_riscv_emit_load (code, RISCV_A1, RISCV_FP, -sizeof(host_mgreg_t), 0);
/* Arg 3 = gregs */
Expand Down Expand Up @@ -240,8 +244,7 @@ mono_arch_get_rethrow_preserve_exception (MonoTrampInfo **info, gboolean aot)
gpointer
mono_arch_get_throw_corlib_exception (MonoTrampInfo **info, gboolean aot)
{
*info = NULL;
return nop_stub (0xaa);
return get_throw_trampoline (384, TRUE, FALSE, FALSE, FALSE, "throw_corlib_exception", info, aot, FALSE);
}

#else
Expand Down
14 changes: 1 addition & 13 deletions src/mono/mono/mini/mini-riscv.c
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Expand Up @@ -3217,19 +3217,7 @@ mono_riscv_emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_typ
static guint8 *
mono_riscv_emit_branch_exc (MonoCompile *cfg, guint8 *code, int opcode, int sreg1, int sreg2, const char *exc_name)
{
// guint8 *p;

// riscv_auipc(code, RISCV_T0, 0);
// // load imm
// riscv_jal (code, RISCV_T1, sizeof (guint64) + 4);
// p = code;
// code += sizeof (guint64);
// riscv_ld (code, RISCV_T1, RISCV_T1, 0);
// // pc + imm
// riscv_add(code, RISCV_T0, RISCV_T0, RISCV_T1);

// *(guint64 *)p = (gsize)code;

riscv_auipc(code, RISCV_T0, 0);
switch (opcode) {
case OP_RISCV_EXC_BEQ:
riscv_bne (code, sreg1, sreg2, 8);
Expand Down