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JIT: Disallow parameters passed in float regs from being enregistered in int regs #99286

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Merged
jakobbotsch merged 4 commits into from
Mar 8, 2024
Merged

JIT: Disallow parameters passed in float regs from being enregistered in int regs #99286

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17f8913
JIT: Validate some reg homing logic
jakobbotsch Mar 5, 2024
048f94c
Stop enregistering problematic case
jakobbotsch Mar 7, 2024
893f01f
Better fix
jakobbotsch Mar 7, 2024
33cdb8e
Clean up
jakobbotsch Mar 7, 2024
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JIT: Validate some reg homing logic 
Just verifying that we never see float reg -> int reg homing on all our
targets...
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@jakobbotsch
jakobbotsch committed Mar 5, 2024
commit 17f8913019672ffcefd9a77aef2ca26cc8b7d2ba
8 changes: 8 additions & 0 deletions src/coreclr/jit/codegencommon.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3795,6 +3795,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, bool* pXtraRegClobbere

regNumber begRegNum = genMapRegArgNumToRegNum(begReg, destMemType);
GetEmitter()->emitIns_Mov(insCopy, size, xtraReg, begRegNum, /* canSkip */ false);
assert(!genIsValidIntReg(xtraReg) || !genIsValidFloatReg(begRegNum));

regSet.verifyRegUsed(xtraReg);

Expand All @@ -3809,6 +3810,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, bool* pXtraRegClobbere
regNumber srcRegNum = genMapRegArgNumToRegNum(srcReg, destMemType);

GetEmitter()->emitIns_Mov(insCopy, size, destRegNum, srcRegNum, /* canSkip */ false);
assert(!genIsValidIntReg(destRegNum) || !genIsValidFloatReg(srcRegNum));

regSet.verifyRegUsed(destRegNum);

Expand Down Expand Up @@ -3860,6 +3862,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, bool* pXtraRegClobbere
regNumber destRegNum = genMapRegArgNumToRegNum(destReg, destMemType);

GetEmitter()->emitIns_Mov(insCopy, size, destRegNum, xtraReg, /* canSkip */ false);
assert(!genIsValidIntReg(destRegNum) || !genIsValidFloatReg(xtraReg));

regSet.verifyRegUsed(destRegNum);
/* mark the beginning register as processed */
Expand Down Expand Up @@ -3934,6 +3937,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, bool* pXtraRegClobbere
// todo -- suppress self move
GetEmitter()->emitIns_R_R_I_I(INS_mov, EA_4BYTE, destRegNum, regNum,
regArgTab[currentArgNum].slot - 1, 0);
assert(!genIsValidIntReg(destRegNum) || !genIsValidFloatReg(regNum));
regArgTab[currentArgNum].processed = true;
regArgMaskLive &= ~genRegMask(regNum);
}
Expand Down Expand Up @@ -4107,6 +4111,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, bool* pXtraRegClobbere
}
#endif
inst_Mov(destMemType, destRegNum, regNum, /* canSkip */ false, size);
assert(!genIsValidIntReg(destRegNum) || !genIsValidFloatReg(regNum));
}

/* mark the argument as processed */
Expand All @@ -4132,6 +4137,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, bool* pXtraRegClobbere
// Emit a shufpd with a 0 immediate, which preserves the 0th element of the dest reg
// and moves the 0th element of the src reg into the 1st element of the dest reg.
GetEmitter()->emitIns_R_R_I(INS_shufpd, emitActualTypeSize(varRegType), destRegNum, nextRegNum, 0);
assert(!genIsValidIntReg(destRegNum) || !genIsValidFloatReg(nextRegNum));
// Set destRegNum to regNum so that we skip the setting of the register below,
// but mark argNum as processed and clear regNum from the live mask.
destRegNum = regNum;
Expand Down Expand Up @@ -4159,6 +4165,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, bool* pXtraRegClobbere
noway_assert(genIsValidFloatReg(nextRegNum));
noway_assert(genIsValidFloatReg(destRegNum));
GetEmitter()->emitIns_Mov(INS_mov, EA_8BYTE, destRegNum, nextRegNum, /* canSkip */ false);
assert(!genIsValidIntReg(destRegNum) || !genIsValidFloatReg(nextRegNum));
}
}
#if defined(TARGET_ARM64) && defined(FEATURE_SIMD)
Expand All @@ -4179,6 +4186,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, bool* pXtraRegClobbere
noway_assert(genIsValidFloatReg(nextRegNum));
noway_assert(genIsValidFloatReg(destRegNum));
GetEmitter()->emitIns_R_R_I_I(INS_mov, EA_4BYTE, destRegNum, nextRegNum, i, 0);
assert(!genIsValidIntReg(destRegNum) || !genIsValidFloatReg(nextRegNum));
}
}
#endif // defined(TARGET_ARM64) && defined(FEATURE_SIMD)
Expand Down