PARL_IO: fix for garbage output at the start of some TX operations

[liebman]

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Pull Request Details 📖

Description

When starting a TX transfer using the PARL_IO peripheral the TX clock was disabled and re-enabled at the start of start_write_bytes_dma. The TRM says that the clock should be re-enabled after tx_start.

Testing

• Logic analyzer
• running a hub75 display via 16bit PARL_IO TX

[bugadani]

Can we test this somehow, like counting expected number of edges with PCNT if the problem is reproducible with narrower outputs?

[liebman]

Can we test this somehow, like counting expected number of edges with PCNT if the problem is reproducible with narrower outputs?

I think thats possible, if we use the valid output and count clocks when valid is high. (thats how I finally isolated it). I'll give that a try.

[liebman]

Added tests. Interestingly the error only happens in async, I added tests for both sync and async for both 8bit and 16bit

[liebman]

Oh - the H2 has only 8 bit PARL_IO!

[liebman]

So the esp32h2 PCNT can't keep up with 20MHz, I reduced the tests to 10MHz and the H2 should be ok. Can't go much lower or the initial bug does not trigger.

[liebman]

No idea why the esp32 test_i2s_loopback test failed - nothing changed there.

[bugadani]

No idea why the esp32 test_i2s_loopback test failed - nothing changed there.

Don't worry about it

[JurajSadel]

Thanks!