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Erase TWAI #2359

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Merged
bugadani merged 6 commits into from
Oct 24, 2024
Merged

Erase TWAI #2359

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8851aaf
Swap order of generics
bugadani Oct 16, 2024
4f64723
Don't refer to Instance in irq handler
bugadani Oct 16, 2024
40675dc
Deduplicate a bit
bugadani Oct 16, 2024
e6b86a3
Take &self
bugadani Oct 16, 2024
ef13070
Reduce nesting
bugadani Oct 16, 2024
0c61001
Erase TWAI instance
bugadani Oct 23, 2024
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Don't refer to Instance in irq handler
  • Loading branch information
@bugadani
bugadani committed Oct 23, 2024
commit 4f647231629bae1a6e1f5c64e0c96a4a6979a89e
133 changes: 65 additions & 68 deletions esp-hal/src/twai/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1165,7 +1165,7 @@ where
/// error states.
pub fn clear_receive_fifo(&self) {
while self.num_available_messages() > 0 {
T::release_receive_fifo();
release_receive_fifo(T::register_block());
}
}

Expand Down Expand Up @@ -1261,7 +1261,7 @@ where
)));
}

Ok(T::read_frame()?)
Ok(read_frame(register_block)?)
}
}

Expand Down Expand Up @@ -1413,15 +1413,6 @@ pub trait Instance: crate::private::Sealed {
&asynch::TWAI_STATE[Self::NUMBER]
}

/// Release the message in the buffer. This will decrement the received
/// message counter and prepare the next message in the FIFO for
/// reading.
fn release_receive_fifo() {
Self::register_block()
.cmd()
.write(|w| w.release_buf().set_bit());
}

/// Write a frame to the peripheral.
fn write_frame(frame: &EspTwaiFrame) {
// Assemble the frame information into the data_0 byte.
Expand Down Expand Up @@ -1494,67 +1485,72 @@ pub trait Instance: crate::private::Sealed {
register_block.cmd().write(|w| w.tx_req().set_bit());
}
}
}

/// Read a frame from the peripheral.
fn read_frame() -> Result<EspTwaiFrame, EspTwaiError> {
let register_block = Self::register_block();
/// Read a frame from the peripheral.
fn read_frame(register_block: &RegisterBlock) -> Result<EspTwaiFrame, EspTwaiError> {
// Read the frame information and extract the frame id format and dlc.
let data_0 = register_block.data_0().read().tx_byte_0().bits();

// Read the frame information and extract the frame id format and dlc.
let data_0 = register_block.data_0().read().tx_byte_0().bits();
let is_standard_format = data_0 & 0b1 << 7 == 0;
let is_data_frame = data_0 & 0b1 << 6 == 0;
let self_reception = data_0 & 0b1 << 4 != 0;
let dlc = data_0 & 0b1111;

let is_standard_format = data_0 & 0b1 << 7 == 0;
let is_data_frame = data_0 & 0b1 << 6 == 0;
let self_reception = data_0 & 0b1 << 4 != 0;
let dlc = data_0 & 0b1111;
if dlc > 8 {
// Release the packet we read from the FIFO, allowing the peripheral to prepare
// the next packet.
release_receive_fifo(register_block);

if dlc > 8 {
// Release the packet we read from the FIFO, allowing the peripheral to prepare
// the next packet.
Self::release_receive_fifo();
return Err(EspTwaiError::NonCompliantDlc(dlc));
}
let dlc = dlc as usize;

return Err(EspTwaiError::NonCompliantDlc(dlc));
}
let dlc = dlc as usize;
// Read the payload from the packet and construct a frame.
let (id, data_ptr) = if is_standard_format {
// Frame uses standard 11 bit id.
let data_1 = register_block.data_1().read().tx_byte_1().bits();
let data_2 = register_block.data_2().read().tx_byte_2().bits();

// Read the payload from the packet and construct a frame.
let (id, data_ptr) = if is_standard_format {
// Frame uses standard 11 bit id.
let data_1 = register_block.data_1().read().tx_byte_1().bits();
let data_2 = register_block.data_2().read().tx_byte_2().bits();
let raw_id: u16 = ((data_1 as u16) << 3) | ((data_2 as u16) >> 5);

let raw_id: u16 = ((data_1 as u16) << 3) | ((data_2 as u16) >> 5);
let id = Id::from(StandardId::new(raw_id).unwrap());
(id, register_block.data_3().as_ptr())
} else {
// Frame uses extended 29 bit id.
let data_1 = register_block.data_1().read().tx_byte_1().bits();
let data_2 = register_block.data_2().read().tx_byte_2().bits();
let data_3 = register_block.data_3().read().tx_byte_3().bits();
let data_4 = register_block.data_4().read().tx_byte_4().bits();

let id = Id::from(StandardId::new(raw_id).unwrap());
(id, register_block.data_3().as_ptr())
} else {
// Frame uses extended 29 bit id.
let data_1 = register_block.data_1().read().tx_byte_1().bits();
let data_2 = register_block.data_2().read().tx_byte_2().bits();
let data_3 = register_block.data_3().read().tx_byte_3().bits();
let data_4 = register_block.data_4().read().tx_byte_4().bits();

let raw_id: u32 = (data_1 as u32) << 21
| (data_2 as u32) << 13
| (data_3 as u32) << 5
| (data_4 as u32) >> 3;

let id = Id::from(ExtendedId::new(raw_id).unwrap());
(id, register_block.data_5().as_ptr())
};
let raw_id: u32 = (data_1 as u32) << 21
| (data_2 as u32) << 13
| (data_3 as u32) << 5
| (data_4 as u32) >> 3;

let mut frame = if is_data_frame {
unsafe { EspTwaiFrame::new_from_data_registers(id, data_ptr, dlc) }
} else {
EspTwaiFrame::new_remote(id, dlc).unwrap()
};
frame.self_reception = self_reception;
let id = Id::from(ExtendedId::new(raw_id).unwrap());
(id, register_block.data_5().as_ptr())
};

// Release the packet we read from the FIFO, allowing the peripheral to prepare
// the next packet.
Self::release_receive_fifo();
let mut frame = if is_data_frame {
unsafe { EspTwaiFrame::new_from_data_registers(id, data_ptr, dlc) }
} else {
EspTwaiFrame::new_remote(id, dlc).unwrap()
};
frame.self_reception = self_reception;

Ok(frame)
}
// Release the packet we read from the FIFO, allowing the peripheral to prepare
// the next packet.
release_receive_fifo(register_block);

Ok(frame)
}

/// Release the message in the buffer. This will decrement the received
/// message counter and prepare the next message in the FIFO for
/// reading.
fn release_receive_fifo(register_block: &RegisterBlock) {
register_block.cmd().write(|w| w.release_buf().set_bit());
}

impl Instance for crate::peripherals::TWAI0 {
Expand Down Expand Up @@ -1772,8 +1768,7 @@ mod asynch {
}
}

fn handle_interrupt<T: Instance>() {
let register_block = T::register_block();
fn handle_interrupt(register_block: &RegisterBlock, async_state: &TwaiAsyncState) {
cfg_if::cfg_if! {
if #[cfg(any(esp32, esp32c3, esp32s2, esp32s3))] {
let intr_enable = register_block.int_ena().read();
Expand All @@ -1794,8 +1789,6 @@ mod asynch {
}
}

let async_state = T::async_state();

if tx_int_status.bit_is_set() {
async_state.tx_waker.wake();
}
Expand All @@ -1813,7 +1806,7 @@ mod asynch {
let _ = rx_queue.try_send(Err(EspTwaiError::EmbeddedHAL(ErrorKind::Overrun)));
}

match T::read_frame() {
match read_frame(register_block) {
Ok(frame) => {
let _ = rx_queue.try_send(Ok(frame));
}
Expand All @@ -1833,12 +1826,16 @@ mod asynch {

#[handler]
pub(super) fn twai0() {
handle_interrupt::<TWAI0>();
let register_block = TWAI0::register_block();
let async_state = TWAI0::async_state();
handle_interrupt(register_block, async_state);
}

#[cfg(twai1)]
#[handler]
pub(super) fn twai1() {
handle_interrupt::<TWAI1>();
let register_block = TWAI1::register_block();
let async_state = TWAI1::async_state();
handle_interrupt(register_block, async_state);
}
}