Skip to content
Merged
Show file tree
Hide file tree
Changes from 2 commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
17 changes: 8 additions & 9 deletions esp32c3-hal/ld/mb-riscv-link.x
Original file line number Diff line number Diff line change
Expand Up @@ -46,12 +46,11 @@ SECTIONS
.rodata :
{
_srodata = .;
*(.srodata .srodata.*);
*(EXCLUDE_FILE (*libriscv-*.rlib:riscv.*) .rodata);
*(EXCLUDE_FILE (*libriscv-*.rlib:riscv.*) .rodata.*);
*(EXCLUDE_FILE (*libriscv_rt-*.rlib:riscv-rt.*) .rodata);
*(EXCLUDE_FILE (*libriscv_rt-*.rlib:riscv-rt.*) .rodata.*);
*(.srodata .srodata.*);
*(.rodata .rodata.*);
*(EXCLUDE_FILE (*libesp_riscv_rt-*.rlib:esp-riscv-rt.*) .rodata);
*(EXCLUDE_FILE (*libesp_riscv_rt-*.rlib:esp-riscv-rt.*) .rodata.*);

/* 4-byte align the end (VMA) of this section.
This is required by LLD to ensure the LMA of the following .data
Expand All @@ -67,12 +66,13 @@ SECTIONS
/* point of the program. */
KEEP(*(.init));
KEEP(*(.init.rust));
KEEP(*(.text.abort));
. = ALIGN(4);
KEEP(*(.trap));
KEEP(*(.trap.rust));

*libriscv-*.rlib:riscv.*(.literal .text .literal.* .text.*);
*libriscv_rt-*.rlib:riscv-rt.*(.literal .text .literal.* .text.*);
*libesp_riscv_rt-*.rlib:esp-riscv-rt.*(.literal .text .literal.* .text.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
Expand Down Expand Up @@ -129,7 +129,7 @@ SECTIONS
*(.sdata .sdata.* .sdata2 .sdata2.*);
*(.data .data.*);
*libriscv-*.rlib:riscv.*(.rodata .rodata.*);
*libriscv_rt-*.rlib:riscv-rt.*(.rodata .rodata.*);
*libesp_riscv_rt-*.rlib:esp-riscv-rt.*(.rodata .rodata.*);
. = ALIGN(4);
_edata = .;
} > REGION_DATA AT>ROM
Expand Down Expand Up @@ -188,9 +188,8 @@ SECTIONS
_stext = .;
*(EXCLUDE_FILE (*libriscv-*.rlib:riscv.*) .text)
*(EXCLUDE_FILE (*libriscv-*.rlib:riscv.*) .text.*)
*(EXCLUDE_FILE (*libriscv_rt-*.rlib:riscv-rt.*) .text)
*(EXCLUDE_FILE (*libriscv_rt-*.rlib:riscv-rt.*) .text.*)
*(.text .text.*);
*(EXCLUDE_FILE (*libesp_riscv_rt-*.rlib:esp-riscv-rt.*) .text)
*(EXCLUDE_FILE (*libesp_riscv_rt-*.rlib:esp-riscv-rt.*) .text.*)
_etext = .;
} > REGION_TEXT AT>ROM

Expand Down
9 changes: 6 additions & 3 deletions esp32c3-hal/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,9 @@ pub mod analog {
extern "C" {
cfg_if::cfg_if! {
if #[cfg(feature = "mcu-boot")] {
// Required for retrieving the entry point address
fn _start();

// Functions from internal ROM
fn cache_suspend_icache() -> u32;
fn cache_resume_icache(val: u32);
Expand Down Expand Up @@ -124,7 +127,7 @@ extern "C" {
#[no_mangle]
#[used]
// Entry point address for the MCUboot image header
static ENTRY_POINT: unsafe fn() -> ! = start_hal;
static ENTRY_POINT: unsafe extern "C" fn() = _start;

#[cfg(feature = "direct-boot")]
#[doc(hidden)]
Expand Down Expand Up @@ -198,8 +201,8 @@ unsafe fn configure_mmu() {
0,
);

let peripherals = peripherals::Peripherals::steal();
peripherals.EXTMEM.icache_ctrl1.modify(|_, w| {
let extmem = unsafe { &*peripherals::EXTMEM::ptr() };
extmem.icache_ctrl1.modify(|_, w| {
w.icache_shut_ibus()
.clear_bit()
.icache_shut_dbus()
Expand Down