Skip to content

async gpio fixes #537

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
MabezDev merged 2 commits into from
May 15, 2023
Merged

async gpio fixes #537

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
9ab34b6
async gpio fixes
MabezDev May 15, 2023
6853aac
add changelog item
MabezDev May 15, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions CHANGELOG.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0

- DMA is supported for SPI3 on ESP32-S3 (#507)
- `change_bus_frequency` is now available on `SpiDma` (#529)
- Fixed a bug where a GPIO interrupt could erroneously fire again causing the next `await` on that pin to instantly return `Poll::Ok` (#537)

### Changed
- Improve examples documentation (#533)
Expand Down
15 changes: 8 additions & 7 deletions esp-hal-common/src/gpio.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1881,6 +1881,8 @@ mod asynch {
P: crate::gpio::Pin + embedded_hal_1::digital::ErrorType,
{
pub fn new(pin: &'a mut P, event: Event) -> Self {
pin.clear_interrupt(); // clear stale interrupt flags, when we await we want to know when an event
// occurs from the await call, not if the pin event has happened recently.
pin.listen(event);
Self { pin }
}
Expand Down Expand Up @@ -1913,27 +1915,21 @@ mod asynch {
type Bank0 = SingleCoreInteruptStatusRegisterAccessBank0;
#[cfg(any(esp32, esp32s2, esp32s3))]
type Bank1 = SingleCoreInteruptStatusRegisterAccessBank1;

let mut intrs = Bank0::pro_cpu_interrupt_status_read() as u64;

#[cfg(any(esp32, esp32s2, esp32s3))]
{
intrs |= (Bank1::pro_cpu_interrupt_status_read() as u64) << 32;
}

// clear interrupts
Bank0GpioRegisterAccess::write_interrupt_status_clear(!0);
#[cfg(any(esp32, esp32s2, esp32s3))]
Bank1GpioRegisterAccess::write_interrupt_status_clear(!0);

while intrs != 0 {
let pin_nr = intrs.trailing_zeros();
cfg_if::cfg_if! {
if #[cfg(any(esp32, esp32s2, esp32s3))] {
if pin_nr < 32 {
Bank0GpioRegisterAccess::set_int_enable(pin_nr as u8, 0, 0, false);
} else {
Bank1GpioRegisterAccess::set_int_enable(pin_nr as u8, 0, 0, false);
Bank1GpioRegisterAccess::set_int_enable((pin_nr - 32) as u8, 0, 0, false);
}
} else {
Bank0GpioRegisterAccess::set_int_enable(pin_nr as u8, 0, 0, false);
Expand All @@ -1942,5 +1938,10 @@ mod asynch {
PIN_WAKERS[pin_nr as usize].wake(); // wake task
intrs &= !(1 << pin_nr);
}

// clear interrupt bits
Bank0GpioRegisterAccess::write_interrupt_status_clear(intrs as u32);
#[cfg(any(esp32, esp32s2, esp32s3))]
Bank1GpioRegisterAccess::write_interrupt_status_clear((intrs >> 32) as u32);
}
}