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17 changes: 17 additions & 0 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -312,6 +312,23 @@ jobs:
- name: check esp32s3-hal (async, i2c)
run: cd esp32s3-hal/ && cargo check --example=embassy_i2c --features=embassy,embassy-time-timg0,async

esp-riscv-rt:
runs-on: ubuntu-latest

steps:
- uses: actions/checkout@v3
- uses: dtolnay/rust-toolchain@v1
with:
target: riscv32imac-unknown-none-elf, riscv32imc-unknown-none-elf
toolchain: nightly
components: rust-src
- uses: Swatinem/rust-cache@v2

- name: Check esp-riscv-rt (imc)
run: cd esp-riscv-rt/ && cargo check --target=riscv32imc-unknown-none-elf -Zbuild-std=core
- name: Check esp-riscv-rt (imac)
run: cd esp-riscv-rt/ && cargo check --target=riscv32imac-unknown-none-elf -Zbuild-std=core

# --------------------------------------------------------------------------
# MSRV

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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -37,6 +37,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Fix Async GPIO not disabling interupts on chips with multiple banks (#572)
- Add unified field-based efuse access
- Add `timer_interrupt` example in ESP32-H2 and refactor `clk_src` configuration (#576)
- Move `esp-riscv-rt` into esp-hal (#578)

### Changed

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2 changes: 1 addition & 1 deletion esp-hal-common/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ embassy-time = { version = "0.1.1", features = ["nightly"], optional = tru
embassy-futures = { version = "0.1.0", optional = true }

# RISC-V
esp-riscv-rt = { version = "0.3.0", optional = true }
esp-riscv-rt = { version = "0.3.0", path = "../esp-riscv-rt", optional = true }
riscv-atomic-emulation-trap = { version = "0.4.0", optional = true }

# Xtensa
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26 changes: 26 additions & 0 deletions esp-riscv-rt/Cargo.toml
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@@ -0,0 +1,26 @@
[package]
name = "esp-riscv-rt"
version = "0.3.0"
edition = "2021"
rust-version = "1.60"
description = "Minimal runtime / startup for RISC-V CPUs from Espressif"
repository = "https://github.com/esp-rs/esp-hal"
license = "MIT OR Apache-2.0"
keywords = ["esp32", "riscv", "runtime", "startup"]
categories = ["embedded", "no-std"]

[dependencies]
riscv = "0.10.1"
riscv-rt-macros = "0.2.0"

[dev-dependencies]
panic-halt = "0.2.0"

[features]
has-mie-mip = []
zero-bss = []
zero-rtc-fast-bss = []
init-data = []
init-rw-text = []
init-rtc-fast-data = []
init-rtc-fast-text = []
32 changes: 32 additions & 0 deletions esp-riscv-rt/README.md
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@@ -0,0 +1,32 @@
# esp-riscv-rt

[![Crates.io](https://img.shields.io/crates/v/esp-riscv-rt?color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp-riscv-rt)
[![docs.rs](https://img.shields.io/docsrs/esp-riscv-rt?color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp-riscv-rt)
![MSRV](https://img.shields.io/badge/MSRV-1.60-blue?style=flat-square)
![Crates.io](https://img.shields.io/crates/l/esp-riscv-rt?style=flat-square)

> Minimal runtime / startup for RISC-V CPUs from Espressif.

Much of the code in this repository originated in the [rust-embedded/riscv-rt](https://github.com/rust-embedded/riscv-rt) repository.

## [Documentation](https://docs.rs/crate/esp-riscv-rt)

## Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.60 and up. It _might_
compile with older versions but that may change in any new patch release.

## License

Licensed under either of:

- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)

at your option.

### Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in
the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without
any additional terms or conditions.
6 changes: 6 additions & 0 deletions esp-riscv-rt/build.rs
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@@ -0,0 +1,6 @@
use std::{env, path::PathBuf};

fn main() {
let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
println!("cargo:rustc-link-search={}", out_dir.display());
}
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