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ESP32-S3 Octal SPIRAM Support #610

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Merged
jessebraham merged 2 commits into from
Jun 22, 2023
Merged

ESP32-S3 Octal SPIRAM Support #610

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ceeab6e
ESP32-S3 Octal SPIRAM Support
bjoernQ Jun 21, 2023
f532c52
Adjust some code comments
bjoernQ Jun 22, 2023
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Adjust some code comments
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@bjoernQ
bjoernQ committed Jun 22, 2023
commit f532c52fa55aa929cb2dcaa0328b27ac3e21985c
17 changes: 7 additions & 10 deletions esp-hal-common/src/soc/esp32s3/psram.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1149,7 +1149,9 @@ pub(crate) mod utils {
mspi_pin_init();
init_psram_pins();
set_psram_cs_timing();
// s_configure_psram_ecc();

// for now we don't support ECC
// "s_configure_psram_ecc();"

// enter MSPI slow mode to init PSRAM device registers
spi_timing_enter_mspi_low_speed_mode(true);
Expand Down Expand Up @@ -1360,9 +1362,8 @@ pub(crate) mod utils {
// Set PSRAM module clock
spi0_timing_config_set_psram_clock(4);

// #if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
// clear_timing_tuning_regs(control_spi1);
// #endif
// for now we don't support tuning the timing
// "clear_timing_tuning_regs(control_spi1);"
}

// Set SPI0 FLASH and PSRAM module clock, din_num, din_mode and extra dummy,
Expand All @@ -1389,9 +1390,8 @@ pub(crate) mod utils {
// Set PSRAM module clock
spi0_timing_config_set_psram_clock(psram_div);

// #if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
// set_timing_tuning_regs_as_required(true);
// #endif
// for now we don't support tuning the timing
// "set_timing_tuning_regs_as_required(true);"
}

fn set_psram_cs_timing() {
Expand Down Expand Up @@ -1426,22 +1426,19 @@ pub(crate) mod utils {

fn init_psram_pins() {
// Set cs1 pin function
// PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[OCT_PSRAM_CS1_IO], FUNC_SPICS1_SPICS1);
unsafe {
let iomux = &*esp32s3::IO_MUX::PTR;
iomux.gpio[OCT_PSRAM_CS1_IO as usize]
.modify(|_, w| w.mcu_sel().variant(FUNC_SPICS1_SPICS1))
}

// Set mspi cs1 drive strength
// PIN_SET_DRV(GPIO_PIN_MUX_REG[OCT_PSRAM_CS1_IO], 3);
unsafe {
let iomux = &*esp32s3::IO_MUX::PTR;
iomux.gpio[OCT_PSRAM_CS1_IO as usize].modify(|_, w| w.fun_drv().variant(3))
}

// Set psram clock pin drive strength
// REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, 3);
set_peri_reg_bits(
SPI0_MEM_DATE_REG,
SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V,
Expand Down