Adding direct vector table hooking support for RISC-V's

.github/workflows/ci.yml

@@ -133,6 +133,8 @@ jobs:
         run: cd esp32c2-hal/ && cargo +nightly check --example=embassy_i2c --features=embassy,embassy-time-systick,async
       - name: check esp32c2-hal (interrupt-preemption)
         run: cd esp32c2-hal/ && cargo check --example=interrupt_preemption --features=interrupt-preemption
+      - name: check esp32c2-hal (direct-vectoring)
+        run: cd esp32c2-hal/ && cargo check --example=direct-vectoring --features=direct-vectoring
       # Ensure documentation can be built
       - name: rustdoc
         run: cd esp32c2-hal/ && cargo doc --features=eh1
@@ -177,6 +179,8 @@ jobs:
         run: cd esp32c3-hal/ && cargo +nightly check --example=embassy_i2c --features=embassy,embassy-time-systick,async
       - name: check esp32c3-hal (interrupt-preemption)
         run: cd esp32c3-hal/ && cargo check --example=interrupt_preemption --features=interrupt-preemption
+      - name: check esp32c3-hal (direct-vectoring)
+        run: cd esp32c3-hal/ && cargo check --example=direct-vectoring --features=direct-vectoring
       # Ensure documentation can be built
       - name: rustdoc
         run: cd esp32c3-hal/ && cargo doc --features=eh1
@@ -219,6 +223,8 @@ jobs:
         run: cd esp32c6-hal/ && cargo +nightly check --example=embassy_i2c --features=embassy,embassy-time-systick,async
       - name: check esp32c6-hal (interrupt-preemption)
         run: cd esp32c6-hal/ && cargo check --example=interrupt_preemption --features=interrupt-preemption
+      - name: check esp32c6-hal (direct-vectoring)
+        run: cd esp32c6-hal/ && cargo check --example=direct-vectoring --features=direct-vectoring
       # Ensure documentation can be built
       - name: rustdoc
         run: cd esp32c6-hal/ && cargo doc --features=eh1
@@ -261,6 +267,8 @@ jobs:
         run: cd esp32h2-hal/ && cargo +nightly check --example=embassy_i2c --features=embassy,embassy-time-systick,async
       - name: check esp32h2-hal (interrupt-preemption)
         run: cd esp32h2-hal/ && cargo check --example=interrupt_preemption --features=interrupt-preemption
+      - name: check esp32h2-hal (direct-vectoring)
+        run: cd esp32h2-hal/ && cargo check --example=direct-vectoring --features=direct-vectoring
       # Ensure documentation can be built
       - name: rustdoc
         run: cd esp32h2-hal/ && cargo doc --features=eh1

CHANGELOG.md

@@ -16,6 +16,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Add a new RMT driver (#653, #667, #695)
 - Implemented calibrated ADC API for ESP32-S3 (#641)
 - Add MCPWM DeadTime configuration (#406)
+- Add feature enabling directly hooking the interrupt vector table
 - Implement sleep with some wakeup methods for `esp32-s3` (#660, #689, #696)
 
 ### Changed

esp-hal-common/Cargo.toml

@@ -103,7 +103,8 @@ embassy = ["embassy-time"]
 embassy-time-systick = []
 embassy-time-timg0   = []
 
-interrupt-preemption = []
+interrupt-preemption = ["esp-riscv-rt/interrupt-preemption"]
+
 
 # Architecture-specific features (intended for internal use)
 riscv  = ["critical-section/restore-state-u8", "esp-riscv-rt", "esp-riscv-rt/zero-bss", "riscv-atomic-emulation-trap"]
@@ -114,6 +115,7 @@ rv-init-data     = ["esp-riscv-rt/init-data", "esp-riscv-rt/init-rw-text"]
 rv-zero-rtc-bss  = ["esp-riscv-rt/zero-rtc-fast-bss"]
 rv-init-rtc-data = ["esp-riscv-rt/init-rtc-fast-data", "esp-riscv-rt/init-rtc-fast-text"]
 
+direct-vectoring = ["esp-riscv-rt/direct-vectoring"]
 # Enable the `impl-register-debug` feature for the selected PAC
 debug = [
     "esp32?/impl-register-debug",

esp-hal-common/src/interrupt/riscv.rs

@@ -69,8 +69,7 @@ pub enum InterruptKind {
     Edge,
 }
 
-/// Enumeration of available CPU interrupts
-///
+/// Enumeration of available CPU interrupts.
 /// It is possible to create a handler for each of the interrupts. (e.g.
 /// `interrupt3`)
 #[repr(u32)]
@@ -198,6 +197,7 @@ mod vectored {
     ///
     /// Note that interrupts still need to be enabled globally for interrupts
     /// to be serviced.
+    #[cfg(not(feature = "direct-vectoring"))]
     pub fn enable(interrupt: Interrupt, level: Priority) -> Result<(), Error> {
         if matches!(level, Priority::None) {
             return Err(Error::InvalidInterruptPriority);
@@ -210,6 +210,30 @@ mod vectored {
         }
         Ok(())
     }
+    /// Enables an interrupt at a given priority, maps it to the given CPU
+    /// interrupt and assigns the given priority.
+    ///
+    /// This can be side-effectful since no guarantees can be made about the
+    /// CPU interrupt not already being in use.
+    ///
+    /// Note that interrupts still need to be enabled globally for interrupts
+    /// to be serviced.
+    #[cfg(feature = "direct-vectoring")]
+    pub unsafe fn enable(
+        interrupt: Interrupt,
+        level: Priority,
+        cpu_interrupt: CpuInterrupt,
+    ) -> Result<(), Error> {
+        if matches!(level, Priority::None) {
+            return Err(Error::InvalidInterruptPriority);
+        }
+        unsafe {
+            map(crate::get_core(), interrupt, cpu_interrupt);
+            set_priority(crate::get_core(), cpu_interrupt, level);
+            enable_cpu_interrupt(cpu_interrupt);
+        }
+        Ok(())
+    }
 
     #[ram]
     unsafe fn handle_interrupts(cpu_intr: CpuInterrupt, context: &mut TrapFrame) {
@@ -368,7 +392,7 @@ pub unsafe extern "C" fn start_trap_rust_hal(trap_frame: *mut TrapFrame) {
         handle_exception(pc, trap_frame);
     } else {
         #[cfg(feature = "interrupt-preemption")]
-        let interrupt_priority = handle_priority();
+        let interrupt_priority = _handle_priority();
         let code = mcause::read().code();
         match code {
             1 => interrupt1(trap_frame.as_mut().unwrap()),
@@ -405,7 +429,7 @@ pub unsafe extern "C" fn start_trap_rust_hal(trap_frame: *mut TrapFrame) {
             _ => DefaultHandler(),
         };
         #[cfg(feature = "interrupt-preemption")]
-        restore_priority(interrupt_priority);
+        _restore_priority(interrupt_priority);
     }
 }
 
@@ -532,7 +556,7 @@ pub fn _setup_interrupts() {
     }
 }
 
-/// Disable the given peripheral interrupt
+/// Disable the given peripheral interrupt.
 pub fn disable(_core: Cpu, interrupt: Interrupt) {
     unsafe {
         let interrupt_number = interrupt as isize;
@@ -578,7 +602,7 @@ pub fn get_status(_core: Cpu) -> u128 {
     }
 }
 
-/// Assign a peripheral interrupt to an CPU interrupt
+/// Assign a peripheral interrupt to an CPU interrupt.
 ///
 /// Great care must be taken when using the `vectored` feature (enabled by
 /// default). Avoid interrupts 1 - 15 when interrupt vectoring is enabled.
@@ -672,7 +696,7 @@ mod classic {
 
     /// Get interrupt priority
     #[inline]
-    pub(super) unsafe fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority {
+    pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority {
         let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
         let intr_prio_base = intr.cpu_int_pri_0.as_ptr();
 
@@ -681,11 +705,10 @@ mod classic {
             .read_volatile();
         core::mem::transmute(prio as u8)
     }
-    #[cfg(all(feature = "interrupt-preemption"))]
-    use procmacros::ram;
-    #[cfg(all(feature = "interrupt-preemption"))]
-    #[ram]
-    pub(super) unsafe fn handle_priority() -> u32 {
+    #[cfg(any(feature = "interrupt-preemption", feature = "direct-vectoring"))]
+    #[no_mangle]
+    #[link_section = ".trap"]
+    pub(super) unsafe extern "C" fn _handle_priority() -> u32 {
         use super::mcause;
         use crate::riscv;
         let interrupt_id: usize = mcause::read().code(); // MSB is whether its exception or interrupt.
@@ -707,9 +730,10 @@ mod classic {
         }
         prev_interrupt_priority
     }
-    #[cfg(all(feature = "interrupt-preemption"))]
-    #[ram]
-    pub(super) unsafe fn restore_priority(stored_prio: u32) {
+    #[cfg(any(feature = "interrupt-preemption", feature = "direct-vectoring"))]
+    #[no_mangle]
+    #[link_section = ".trap"]
+    pub(super) unsafe extern "C" fn _restore_priority(stored_prio: u32) {
         use crate::riscv;
         unsafe {
             riscv::interrupt::disable();
@@ -739,7 +763,7 @@ mod plic {
     const PLIC_MXINT_TYPE_REG: u32 = DR_REG_PLIC_MX_BASE + 0x4;
     const PLIC_MXINT_CLEAR_REG: u32 = DR_REG_PLIC_MX_BASE + 0x8;
     const PLIC_MXINT0_PRI_REG: u32 = DR_REG_PLIC_MX_BASE + 0x10;
-    #[cfg(feature = "interrupt-preemption")]
+    #[cfg(any(feature = "interrupt-preemption", feature = "direct-vectoring"))]
     const PLIC_MXINT_THRESH_REG: u32 = DR_REG_PLIC_MX_BASE + 0x90;
     /// Enable a CPU interrupt
     pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) {
@@ -797,7 +821,7 @@ mod plic {
 
     /// Get interrupt priority
     #[inline]
-    pub(super) unsafe fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority {
+    pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority {
         let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32;
 
         let cpu_interrupt_number = cpu_interrupt as isize;
@@ -806,11 +830,10 @@ mod plic {
             .read_volatile();
         core::mem::transmute(prio as u8)
     }
-    #[cfg(all(feature = "interrupt-preemption"))]
-    use procmacros::ram;
-    #[cfg(all(feature = "interrupt-preemption"))]
-    #[ram]
-    pub(super) unsafe fn handle_priority() -> u32 {
+    #[cfg(any(feature = "interrupt-preemption", feature = "direct-vectoring"))]
+    #[no_mangle]
+    #[link_section = ".trap"]
+    pub(super) unsafe extern "C" fn _handle_priority() -> u32 {
         use super::mcause;
         use crate::riscv;
         let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32;
@@ -829,9 +852,10 @@ mod plic {
         }
         prev_interrupt_priority
     }
-    #[cfg(all(feature = "interrupt-preemption"))]
-    #[ram]
-    pub(super) unsafe fn restore_priority(stored_prio: u32) {
+    #[cfg(any(feature = "interrupt-preemption", feature = "direct-vectoring"))]
+    #[no_mangle]
+    #[link_section = ".trap"]
+    pub(super) unsafe extern "C" fn _restore_priority(stored_prio: u32) {
         use crate::riscv;
         unsafe {
             riscv::interrupt::disable();

esp-riscv-rt/Cargo.toml

@@ -17,10 +17,12 @@ riscv-rt-macros = "0.2.0"
 panic-halt = "0.2.0"
 
 [features]
+direct-vectoring = []
+interrupt-preemption = []
 has-mie-mip = []
 zero-bss = []
 zero-rtc-fast-bss = []
 init-data = []
 init-rw-text = []
 init-rtc-fast-data = []
-init-rtc-fast-text = []
+init-rtc-fast-text = []