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@bjoernQ bjoernQ commented Jul 3, 2023

Adds support to run code on ULP-RISCV (ESP32-S2 / ESP32-S3) and LP core (ESP32-C6)

While there are examples this doesn't add a completely useable feature yet.
It's meant to facilitate working on enabling proper support for the ESP32-C6 LP core for now.

Better examples and documentation will get added while working on that

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LGTM! My other comment was just something to try out, not worth blocking this initial impl :). I'll let you play around with it and make the decision.

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bjoernQ commented Jul 3, 2023

Using #[link_section = ".rtc_slow.text"] kind of worked when I also use &CODE in the code - otherwise it's removed even when built in debug mode 🤔

While it's still an interesting idea for the later (real) implementation I guess it's better to keep it simple and explicit for now

Thanks for the quick review

@bjoernQ bjoernQ merged commit 996da27 into esp-rs:main Jul 3, 2023
@bjoernQ bjoernQ deleted the basic-lp-core branch July 3, 2023 14:15
playfulFence pushed a commit to playfulFence/esp-hal that referenced this pull request Sep 26, 2023
* Bare-bones support to run code on ULP-RV/LP core

* Add CHANGELOG.md entry
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