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[CIR][CIRGen][Builtin][Neon] Lower neon_vsetq_lane_f64 #1251

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Merged
merged 2 commits into from
Jan 6, 2025
Merged

[CIR][CIRGen][Builtin][Neon] Lower neon_vsetq_lane_f64 #1251

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b8dae5f
[CIR][CIRGen][Builtin][Neon] Lower neon_vsetq_lane_f64
AmrDeveloper Dec 21, 2024
a813705
Fix the lit test
AmrDeveloper Dec 24, 2024
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10 changes: 7 additions & 3 deletions clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3690,9 +3690,13 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
case NEON::BI__builtin_neon_vset_lane_f64:
// The vector type needs a cast for the v1f64 variant.
llvm_unreachable("NEON::BI__builtin_neon_vset_lane_f64 NYI");
case NEON::BI__builtin_neon_vsetq_lane_f64:
// The vector type needs a cast for the v2f64 variant.
llvm_unreachable("NEON::BI__builtin_neon_vsetq_lane_f64 NYI");
case NEON::BI__builtin_neon_vsetq_lane_f64: {
Ops.push_back(emitScalarExpr(E->getArg(2)));
Ops[1] = builder.createBitcast(
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@ghehg ghehg Jan 2, 2025 •
edited
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IMO
To reduce code duplication which OG had, We could consider extracting
`
Ops.push_back(emitScalarExpr(E->getArg(2)));

return builder.createcir::VecInsertOp(getLoc(E->getExprLoc()), Ops[1],
Ops[0], Ops[2]);
`
into a helper function in future case like this.

Ops[1], cir::VectorType::get(&getMLIRContext(), DoubleTy, 2));
return builder.create<cir::VecInsertOp>(getLoc(E->getExprLoc()), Ops[1],
Ops[0], Ops[2]);
}

case NEON::BI__builtin_neon_vget_lane_i8:
case NEON::BI__builtin_neon_vdupb_lane_i8:
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12 changes: 12 additions & 0 deletions clang/test/CIR/CodeGen/AArch64/neon-misc.c
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Expand Up @@ -137,6 +137,18 @@ float32x4_t test_vsetq_lane_f32(float32_t a, float32x4_t b) {
// LLVM: [[INTRN_RES:%.*]] = insertelement <4 x float> [[B]], float [[A]], i32 3
// LLVM: ret <4 x float> [[INTRN_RES]]

float64x2_t test_vsetq_land_f64(float64_t a, float64x2_t b) {
return vsetq_lane_f64(a, b, 0);
}

// CIR-LABEL: test_vsetq_land_f64
// CIR: [[IDX:%.*]] = cir.const #cir.int<0> : !s32i
// CIR: {{%.*}} = cir.vec.insert {{%.*}}, {{%.*}}[[[IDX]] : !s32i] : !cir.vector<!cir.double x 2>

// LLVM: {{.*}}test_vsetq_land_f64(double{{.*}}[[A:%.*]], <2 x double>{{.*}}[[B:%.*]])
// LLVM: [[INTRN_RES:%.*]] = insertelement <2 x double> [[B]], double [[A]], i32 0
// LLVM: ret <2 x double> [[INTRN_RES]]

uint8_t test_vget_lane_u8(uint8x8_t a) {
return vget_lane_u8(a, 7);
}
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