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[InstCombine] Avoid folding select(umin(X, Y), X) with min/max values in false arm #143020

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Merged
dtcxzyw merged 13 commits into from
Jun 14, 2025
Merged

[InstCombine] Avoid folding select(umin(X, Y), X) with min/max values in false arm #143020

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084efd9
Prototype fix
thevar1able Jun 5, 2025
1b3e662
Fix formatting
thevar1able Jun 5, 2025
d87b193
Move checks to FoldOpIntoSelect
thevar1able Jun 5, 2025
69eaf81
Fix formatting
thevar1able Jun 5, 2025
8240c6c
Apply suggested fix
thevar1able Jun 7, 2025
8a7663b
Update expected output
thevar1able Jun 11, 2025
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thevar1able Jun 11, 2025
22ef252
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d424540
Update tests assertions
thevar1able Jun 11, 2025
304cf20
Revert suggested fix
thevar1able Jun 11, 2025
1165581
Update tests assertions
thevar1able Jun 11, 2025
0d48fc4
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thevar1able Jun 13, 2025
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@thevar1able
thevar1able committed Jun 11, 2025
commit 22ef2528d9299e9b02ef5b5535f6c8900bdf377d
76 changes: 62 additions & 14 deletions llvm/test/Transforms/InstCombine/select.ll
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Expand Up @@ -5048,17 +5048,65 @@ define <2 x ptr> @select_freeze_constant_expression_vector_gep(i1 %cond, <2 x pt
ret <2 x ptr> %sel
}

; declare i8 @llvm.umin.i8(i8, i8)
;
; define i8 @no_fold_masked_min(i8 %acc, i8 %val, i8 %mask) {
; ; CHECK-LABEL: @no_fold_masked_min(
; ; CHECK-NEXT: [[COND:%.*]] = icmp eq i8 [[MASK:%.*]], 0
; ; CHECK-NEXT: [[MASKED_VAL:%.*]] = select i1 [[COND:%.*]], i8 [[VAL:%.*]], i8 -1
; ; CHECK-NEXT: [[RES:%.*]] = call i8 @llvm.umin.i8(i8 [[ACC:%.*]], i8 [[MASKED_VAL:%.*]])
; ; CHECK-NEXT: ret i8 [[RES]]
; ;
; %cond = icmp eq i8 %mask, 0
; %masked_val = select i1 %cond, i8 %val, i8 -1
; %res = call i8 @llvm.umin.i8(i8 %acc, i8 %masked_val)
; ret i8 %res
; }
declare i8 @llvm.umin.i8(i8, i8)

define i8 @no_fold_masked_min(i8 %acc, i8 %val, i8 %mask) {
; CHECK-LABEL: @no_fold_masked_min(
; CHECK-NEXT: [[COND:%.*]] = icmp eq i8 [[MASK:%.*]], 0
; CHECK-NEXT: [[MASKED_VAL:%.*]] = select i1 [[COND]], i8 [[VAL:%.*]], i8 -1
; CHECK-NEXT: [[RES:%.*]] = call i8 @llvm.umin.i8(i8 [[ACC:%.*]], i8 [[MASKED_VAL]])
; CHECK-NEXT: ret i8 [[RES]]
;
%cond = icmp eq i8 %mask, 0
%masked_val = select i1 %cond, i8 %val, i8 -1
%res = call i8 @llvm.umin.i8(i8 %acc, i8 %masked_val)
ret i8 %res
}

define void @no_fold_masked_min_loop(ptr nocapture readonly %vals, ptr nocapture readonly %masks, ptr nocapture %out, i64 %n) {
; CHECK-LABEL: @no_fold_masked_min_loop(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[NEXT_INDEX:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[ACC:%.*]] = phi i8 [ -1, [[ENTRY]] ], [ [[RES:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[VAL_PTR:%.*]] = getelementptr inbounds i8, ptr [[VALS:%.*]], i64 [[INDEX]]
; CHECK-NEXT: [[MASK_PTR:%.*]] = getelementptr inbounds i8, ptr [[MASKS:%.*]], i64 [[INDEX]]
; CHECK-NEXT: [[VAL:%.*]] = load i8, ptr [[VAL_PTR]], align 1
; CHECK-NEXT: [[MASK:%.*]] = load i8, ptr [[MASK_PTR]], align 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i8 [[MASK]], 0
; CHECK-NEXT: [[MASKED_VAL:%.*]] = select i1 [[COND]], i8 [[VAL]], i8 -1
; CHECK-NEXT: [[RES]] = call i8 @llvm.umin.i8(i8 [[ACC]], i8 [[MASKED_VAL]])
; CHECK-NEXT: [[NEXT_INDEX]] = add i64 [[INDEX]], 1
; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXT_INDEX]], [[N:%.*]]
; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: store i8 [[RES]], ptr [[OUT:%.*]], align 1
; CHECK-NEXT: ret void
;

entry:
br label %loop

loop:
%index = phi i64 [0, %entry], [%next_index, %loop]
%acc = phi i8 [255, %entry], [%res, %loop]

%val_ptr = getelementptr inbounds i8, ptr %vals, i64 %index
%mask_ptr = getelementptr inbounds i8, ptr %masks, i64 %index

%val = load i8, ptr %val_ptr, align 1
%mask = load i8, ptr %mask_ptr, align 1

%cond = icmp eq i8 %mask, 0
%masked_val = select i1 %cond, i8 %val, i8 -1
%res = call i8 @llvm.umin.i8(i8 %acc, i8 %masked_val)

%next_index = add i64 %index, 1
%done = icmp eq i64 %next_index, %n
br i1 %done, label %exit, label %loop

exit:
store i8 %res, ptr %out, align 1
ret void
}
2 changes: 0 additions & 2 deletions llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
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Expand Up @@ -326,8 +326,6 @@ cleanup:
ret i1 %retval.0
}

; From https://github.com/llvm/llvm-project/issues/139050.
; FIXME: This should be vectorized.
define i8 @masked_min_reduction(ptr %data, ptr %mask) {
; CHECK-LABEL: @masked_min_reduction(
; CHECK-NEXT: entry:
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