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For reasons I haven't determined, gld sometimes generates 5 sections in the output. For example, ttn-abp.ino when compiled for region IN866 has 5 sections (but 4 for other regions)
Treating ./ttn-abp.ino.elf as ELF file
ELF: section 0: vaddr(8005000) paddr(8005000) size(a000) vend(800f000) offset(1000) fsize(a000) flags(5)
ELF: section 1: vaddr(800f000) paddr(800f000) size(34) vend(800f034) offset(b000) fsize(34) flags(6)
ELF: section 2: vaddr(20000000) paddr(800f034) size(118) vend(20000118) offset(c000) fsize(118) flags(6)
ELF: section 3: vaddr(800f14c) paddr(800f14c) size(a0) vend(800f1ec) offset(c14c) fsize(a0) flags(4)
ELF: section 4: vaddr(20000118) paddr(20000118) size(1030) vend(20001148) offset(d118) fsize(0) flags(6)
There was a hard-coded stop (for no good reason -- it was historical) at 4 sections; so the above would fail to complete a compile with the 3.0.0 or 3.0.1 MCCI STM32 BSP.
Remove the hard stop.
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