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Commits on Mar 14, 2019

• Fixed the size of data_reg nets

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  pdabholkar

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  e42977b

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Commits on Mar 8, 2019

• Testbench updates

  alexforencich

  committed
  013e882

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• merged changes in axis

  alexforencich

  committed
  4d3036b

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• Properly handle width of 1

  alexforencich

  committed
  414f091

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• Remove unused code

  alexforencich

  committed
  b1f3a74

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• Add AXI stream frame length measurement module and testbenches

  alexforencich

  committed
  d2df971

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• Testbench updates

  alexforencich

  committed
  e0f7404

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Commits on Feb 28, 2019

• Add AXI stream broadcast module and testbench

  alexforencich

  committed
  b60886a

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Commits on Feb 7, 2019

• Enable bitstream compression in example designs

  alexforencich

  committed
  cd6b87e

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Commits on Feb 6, 2019

• Swap out PHY in VCU118 example design

  alexforencich

  committed
  52058cb

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Commits on Feb 1, 2019

• Update readme

  alexforencich

  committed
  22b3d05

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• Add bit reverse support to serdes endpoint

  alexforencich

  committed
  c1fe89d

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• Add 10G Ethernet MAC/PHY combination modules and testbenches

  alexforencich

  committed
  ec38440

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• Update testbench

  alexforencich

  committed
  5f6e7f7

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• Add start packet strobe timing outputs to MAC modules

  alexforencich

  committed
  e644ce3

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Commits on Jan 23, 2019

• Add zero IFG forced offset start test

  alexforencich

  committed
  a743f6f

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• Add force offset start parameter

  alexforencich

  committed
  5b2d4fd

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Commits on Jan 22, 2019

• Fix off-by-one error in control character checks

  alexforencich

  committed
  4d2090a

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• Fix DIC implementation in testbench

  alexforencich

  committed
  92df377

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• Simplify lane swapping code

  alexforencich

  committed
  9ae60dc

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• Adjustment to scrambler bypass

  alexforencich

  committed
  54e31c5

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• Report error for invalid encoding

  alexforencich

  committed
  6238ed5

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• Remove unused code

  alexforencich

  committed
  e784900

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Commits on Jan 19, 2019

• Update readme

  alexforencich

  committed
  a060d2e

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Commits on Jan 18, 2019

• Switch out Xilinx PHY core in ExaNIC X10 example design

  alexforencich

  committed
  07b4efa

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• Switch out Xilinx PHY core in ADM-PCIE-9V3 example design

  alexforencich

  committed
  0bbe062

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• Fix input clock period settings

  alexforencich

  committed
  2e29aea

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Commits on Jan 17, 2019

• Add 10G Ethernet PHY modules and testbenches

  alexforencich

  committed
  dbbbc28

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• Add XGMII 10GBASE-R encoder and decoder modules and testbenches

  alexforencich

  committed
  91553e6

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• Add BASE-R SERDES endpoint model

  alexforencich

  committed
  c9752f2

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• Clamp ifg_cnt at zero

  alexforencich

  committed
  5fbd675

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Commits on Jan 16, 2019

• Add short IFG tests

  alexforencich

  committed
  128dc29

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• Properly handle short IFG

  alexforencich

  committed
  ea02b6c

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• Remove unreachable code

  alexforencich

  committed
  32d889b

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• Move ifg parameter

  alexforencich

  committed
  bf94ef5

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