This repository is created to accommodate the verilog, matlab and python scripts required for the course project for Circuits and System Design module at the Department of Electronic and Telecommunication Engineering at the Univeristy of Moratuwa. Contributors are Ashwin de Silva, Praga SV, Sachini Hewage and Chinthani Kumaradasa.
The ISA used for the design can be found here.
https://drive.google.com/open?id=1Oxo3c4O4xeMmX2UtsbSlmtF7uGvVImrR
The control store LUT, the ALU control signals and the B bus decoder control signals can be found here.
https://drive.google.com/open?id=1phKuFeZmdkYVxINu6qEn8kiF5Zhd-Fz6Cjh_C46X4Tg
A video of the implementation can be found here.