bug in src/deprecated/clock_divider.sv: bitwise-and bit-width mismatch

[ljbrooks]

Not sure if this is maintained or not,

source file link clock_divider.sv

This could be a potential bug, or should be fixed by an explicit bit select on reg_ext_gate_sync.

the LHS is a one bit logic, RHS is bitwise-and of a 1-bit logic vs a 2-bit logic.

Either a bug, or should be fixed for clarity.

   logic               s_clk_out;
   logic               s_clock_enable;   <--- one bit 
   logic               s_clock_enable_gate; <--- one bit
   logic               s_clk_div_valid;

   logic [7:0]         reg_clk_div;
   logic               s_clk_div_valid_sync;

   logic               s_rstn_sync;

   logic [1:0]         reg_ext_gate_sync;  <--- two bits

    assign s_clock_enable_gate =  s_clock_enable & reg_ext_gate_sync;   <---- 1 bit BITWISE_AND 2 bits and assign to a 1 bit