Adding scripts for PyJTAG and short Readme

esp32/PyJTAG/Readme.txt

@@ -0,0 +1,37 @@
+Short readme for how to use the PyJTAG.
+Detailed information are here: https://pycomiot.atlassian.net/wiki/spaces/FIR/pages/966295564/Usage+of+PyJTAG
+
+Setup the PyJTAG board's switches:
+ESP32 JTAG: all turned ON
+ESP32 B.LOADER: all turned ON except SAFE_BOOT_SW which is OFF
+TO LTE UART 1/2: does not matter
+CURRENT SHUNTS: connected
+
+Generally follow these rules to setup JTAG debugging on your OS: https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/jtag-debugging/index.html
+
+(Download link of OpenOCD for ESP32 from Espressif: https://github.com/espressif/openocd-esp32/releases)
+
+Running OpenOCD assuming the current location is "esp32" folder in Firmware-Development repository:
+Start OpenOCD: "PATH_TO_OPENOCD/bin/openocd -s PATH_TO_OPENOCD/share/openocd/scripts -s PyJTAG -f PyJTAG/interface/ftdi/esp32-pycom.cfg -f PyJTAG/board/esp32-pycom.cfg"
+Output should be like: 
+
+Open On-Chip Debugger  v0.10.0-esp32-20191114 (2019-11-14-14:15)
+Licensed under GNU GPL v2
+For bug reports, read
+	http://openocd.org/doc/doxygen/bugs.html
+none separate
+adapter speed: 20000 kHz
+Info : Configured 2 cores
+Info : Listening on port 6666 for tcl connections
+Info : Listening on port 4444 for telnet connections
+Error: type 'esp32' is missing virt2phys
+Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
+Info : clock speed 20000 kHz
+Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
+Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
+Info : Listening on port 3333 for gdb connections
+
+
+When OpenOCD is running start GDB from "esp32" folder assuming you have a FIPY:
+"xtensa-esp32-elf-gdb -x gdbinit build/FIPY/release/application.elf"
+

esp32/PyJTAG/board/esp32-pycom.cfg

@@ -0,0 +1,2 @@
+set ESP32_FLASH_VOLTAGE 3.3
+source [find target/esp32-pycom.cfg]

esp32/PyJTAG/interface/ftdi/esp32-pycom.cfg

@@ -0,0 +1,35 @@
+#
+# Driver for the FT4232HL JTAG chip on the Pycom's PyJTAG board
+#
+
+
+interface ftdi
+ftdi_vid_pid 0x0403 0x6011
+
+# interface 1 is the uart
+ftdi_channel 0
+
+# TCK, TDI, TDO, TMS: ADBUS0-3
+# LEDs: ACBUS4-7
+
+ftdi_layout_init 0x0008 0xf00b
+#ftdi_layout_signal LED -data 0x1000
+#ftdi_layout_signal LED2 -data 0x2000
+#ftdi_layout_signal LED3 -data 0x4000
+#ftdi_layout_signal LED4 -data 0x8000
+
+# ESP32 series chips do not have a TRST input, and the SRST line is connected
+# to the EN pin. 
+# The target code doesn't handle SRST reset properly yet, so this is
+# commented out:
+# ftdi_layout_signal nSRST -oe 0x0020
+
+reset_config none
+
+# The speed of the JTAG interface, in KHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter_khz 20000

esp32/PyJTAG/target/esp32-pycom.cfg

@@ -0,0 +1,69 @@
+# The ESP32 only supports JTAG.
+transport select jtag
+
+# Source the ESP common configuration file
+source [find target/esp_common.cfg]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME esp32
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x120034e5
+}
+
+if { [info exists ESP32_ONLYCPU] } {
+	set _ONLYCPU $ESP32_ONLYCPU
+} else {
+	set _ONLYCPU 3
+}
+
+if { [info exists ESP32_FLASH_VOLTAGE] } {
+	set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE
+} else {
+	set _FLASH_VOLTAGE 3.3
+}
+
+set _TARGETNAME $_CHIPNAME
+set _CPU0NAME cpu0
+set _CPU1NAME cpu1
+set _TAPNAME $_CHIPNAME.$_CPU0NAME
+
+jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
+if { $_ONLYCPU != 1 } {
+	jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID
+} else {
+	jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID
+}
+
+if { $_RTOS == "none" } {
+	target create $_TARGETNAME esp32 -endian little -chain-position $_TAPNAME
+} else {
+	target create $_TARGETNAME esp32 -endian little -chain-position $_TAPNAME -rtos $_RTOS
+}
+
+configure_esp_workarea $_TARGETNAME 0x40090000 0x3400 0x3FFC0000 0x6000
+configure_esp_flash_bank $_TARGETNAME $_TARGETNAME $_FLASH_SIZE
+
+esp32 flashbootstrap $_FLASH_VOLTAGE
+esp32 maskisr on
+if { $_SEMIHOST_BASEDIR != "" } {
+	esp32 semihost_basedir $_SEMIHOST_BASEDIR
+}
+if { $_FLASH_SIZE == 0 } {
+	gdb_breakpoint_override hard
+}
+
+# special function to program ESP32, it differs from the original 'program' that
+# it verifies written image by reading flash directly, instead of reading memory mapped flash regions
+proc program_esp32 {filename args} {
+	program_esp $filename $args
+}
+
+add_help_text program_esp32 "write an image to flash, address is only required for binary images. verify, reset, exit are optional"
+add_usage_text program_esp32 "<filename> \[address\] \[verify\] \[reset\] \[exit\]"
+