Yosys Open SYnthesis Suite

Resources to install NixOS bare metal on Apple Silicon Macs

A tool to include drawio diagrams in your mdbook

Verilator open-source SystemVerilog simulator and lint system

PyTic - An Object-Oriented Python Wrapper for Pololu Tic Stepper Drivers

A plugin for circuit notation

Nix Packages collection

nextpnr portable FPGA place and route tool

Main repository for Vispy

A sub-micrometer 3D motion control plattform.

CadQuery and CQ-editor flake, closely follows master

Build your hardware, easily!

Python library using the Futhark C backend via CFFI

Programmer for the Lattice ECP5 series, making use of FTDI based adaptors

Small footprint and configurable Ethernet core

Tiny Tapeout GDS Action (using OpenLane)

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

SystemVerilog support for Yosys

The next generation of OpenLane, rewritten from scratch with a modular architecture