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Add ITNS field to NVIC peripheral #422

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Merged
merged 2 commits into from
Nov 12, 2022
Merged

Add ITNS field to NVIC peripheral #422

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05ddb44
add itns field to NVIC perph
sphw Feb 16, 2022
9bff0c8
fix and cleanup offsets in nvic
sphw Mar 15, 2022
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12 changes: 10 additions & 2 deletions src/peripheral/nvic.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,15 @@ pub struct RegisterBlock {
#[cfg(armv6m)]
_reserved4: [u32; 16],

_reserved5: [u32; 48],
_reserved5: [u32; 16],

#[cfg(armv8m)]
/// Interrupt Target Non-secure (only present on Arm v8-M)
pub itns: [RW<u32>; 16],
#[cfg(not(armv8m))]
_reserved6: [u32; 16],

_reserved7: [u32; 16],

/// Interrupt Priority
///
Expand Down Expand Up @@ -67,7 +75,7 @@ pub struct RegisterBlock {
pub ipr: [RW<u32>; 8],

#[cfg(not(armv6m))]
_reserved6: [u32; 580],
_reserved8: [u32; 580],

/// Software Trigger Interrupt
#[cfg(not(armv6m))]
Expand Down