3-stage RV32IMACZb* processor with debug

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

ASIC implementation flow infrastructure, successor to OpenLane

Circuit IR Compilers and Tools

Chisel: A Modern Hardware Design Language

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

Verilator open-source SystemVerilog simulator and lint system

Yosys Open SYnthesis Suite

Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications

Implement Tiny YOLO v3 on ZYNQ

Machine learning on FPGAs using HLS

Dataflow compiler for QNN inference on FPGAs

Verilog AXI components for FPGA implementation

Posit Arithmetic Cores generated with FloPoCo

Simple 3-stage pipeline RISC-V processor

Online browser-based RTS game

[FPGA'26 Best Paper] KANELÉ: Kolmogorov–Arnold Networks for Efficient LUT-based Evaluation

synthesiseable ieee 754 floating point library in verilog

Bus bridges and other odds and ends

Brushless servo and quadrupedal robot

Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database

An incremental parsing system for programming tools

Multi-platform nightly builds of open source digital design and verification tools

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

DNN Compiler for Heterogeneous SoCs

An open-source 32-bit RISC-V soft-core processor

🌸 A command-line fuzzy finder

Patch to add support to Alacritty for graphics (Sixel and iTerm2 protocols)

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.